Product specifications

DA100 (50Hz) Chassis – Article for Television Magazine
Page 56 of 80
Sharp Electronics (UK) Limited - March 2003
Video and Synchronisation Processor
This IC is a member of the ‘Micronas’ VDP 31xxB IC family. These are high-quality video processors
that allow the economic integration of features in all classes of TV sets. The VDP 31xxB family is
based on functional blocks contained in the two previous chips form Micronas – the VPC3200A Video
Processor and DDP3300A Display and Deflection Processor.
Figure 55: Internal Architecture of IC801 (VDP 3120)
The VDP 31xxB contains the entire video, display, and deflection processing for 4:3 and 16:9
television’s operating at either 50 or 60Hz featuring:
• 2H adaptive Comb-filter
• Scan Velocity Modulator
• 1H Comb-filter
• Colour Transient Improvement.
• RGB Insertion
• CRT Control
• Programmable RGB Matrix
• 4 composite inputs (one for S-VHS)
• Composite video & sync output
• Horizontal scaling (0.25 to 4)
• Panorama vision
• Black level expander
• Dynamic peaking
• Soft-limiter (gamma correction)
• Picture vertical generator
• High-performance H/V deflection
• Separate Analogue to Digital Converter for
CRT measurements
• EHT compensation
• One 20.25 MHz crystal (for all systems),
few external components
• Embedded RISC controller (80 MIPS)
• I
2C-Bus Interface
• Single 5 V power supply
Analogue Front End
This block provides the analogue interfaces to all video inputs and mainly carries out analogue-to
digital conversion for the following digital video processing.
Most of the functional blocks in the front-end are digitally controlled (clamping, AGC, and clock-DCO).
The control loops are closed by the Fast Processor (‘FP’) embedded in the decoder.
Revision 2