Specifications

Circuit Diagrams and PWB Layouts
49ES1E AA 7.
SSB: Control-Memory Interface (SDRAM)
1M x 16
1M x 16
1M x 16
1M x 16
BANK
SELECT
OUTPUT BUFFER
VSS VSSQ
TIMING REGISTER
NC
ADDRESS REGISTER
LCKE
BURST LENGTH
LATENCY &
DECODER
COLUMN
LWCBR
LCAS
LWE
REGISTER
COL. BUFFER
LQDM
ROW DECODER
REFRESH COUNTER
ROW BUFFER
LDQM
LWE
I/O CONTROL
SENSE AMP
LRAS
VDD VDDQ
LCBR
DATA INPUT
REGISTER
PROGRAMMING
LRAS
LCBR
SDRAM
2733
100n
F730 D2
7730 B6
N.C.
2734 B7
3737 E4
5730 A6
5731 A7
B
C
D
E
F
2730 B6
2731 B6
2732 B5
78
A
7300-I B2
1 3452
F
A
220R
E
CONTROL-MEMORY INTERFACE (SDRAM)
6
76
2733 B7
1
B
C
D
4
8
5
100Mhz /
220R
32
100Mhz /
2731
100n
5730
2732
VDDE
100n 100n
2734
52
16 WE_
3737
33R
RAS_
39 UDQM
11427394349
28 41 54 6 12 46
47
DQ12 48
DQ13 50
DQ14 51
DQ15 53
5DQ2
7DQ3
8DQ4
10DQ5
11DQ6
13DQ7
DQ8 42
DQ9 44
LDQM15
36
NC|RFU 40
18
26
A429
A530
A631
A732
A833
A934
20 BA0
BA121
17 CAS_
CKE37
CLK38
CS_19
2DQ0
4DQ1
DQ10 45
DQ11
SDRAM-RASN
A14
SDRAM-UDQM
A23
SDRAM-WEN
7730
K4S641632D
A023
A124
22 A10|AP
A1135
A225
A3
SDRAM-D10
B15
SDRAM-D11
C15
SDRAM-D12
C16
SDRAM-D13
A16
SDRAM-D14
A17
SDRAM-D15
C26
SDRAM-D2
A25
SDRAM-D3
C24
SDRAM-D4
B24
SDRAM-D5
A24
SDRAM-D6
C23
SDRAM-D7
B14
SDRAM-D8
C14
SDRAM-D9
B23
SDRAM-LDQM
A22
SDRAM-A3
C18
SDRAM-A4
B18
SDRAM-A5
A18
SDRAM-A6
C17
SDRAM-A7
B17
SDRAM-A8
C11
SDRAM-A9
B21
SDRAM-BS0
A21
SDRAM-BS1
C22
SDRAM-CASN
C12
SDRAM-CKE
C13
SDRAM-CLK-IN
A13
SDRAM-CLK-OUT
C21
SDRAM-CSN
B26
SDRAM-D0
C25
SDRAM-D1
A15
ADOC
7300-I
B20
SDRAM-A0
A20
SDRAM-A1
C20
SDRAM-A10
A12
SDRAM-A11
B12
SDRAM-A12
C19
SDRAM-A2
A19
VDDE
5731
2730
F730
100n
SD(11)
SD(10)
SD(9)
SD(8)
SD(7)
SD(6)
SD(5)
SD(4)
SD(3)
SD(2)
SD(1)
SD(0)
SD(0)
SD(1)
SD(2)
SD(3)
SD(4)
SD(5)
SD(6)
SD(7)
SD(8)
SD(9)
SD(10)
SD(11)
SD(12)
SD(13)
SD(14)
SD(15)
SA(11)
SA(10)
SA(9)
SA(8)
SA(7)
SA(6)
SA(5)
SA(4)
SA(3)
SA(2)
SA(1)
SA(0)
SA(0)
SA(1)
SA(2)
SA(3)
SA(4)
SA(5)
SA(6)
SA(7)
SA(8)
SA(9)
SA(10)
SA(11)
SD(15)
SD(14)
SD(13)
SD(12)
CL 36532058_034.eps
030903
3139 123 5536.2