User's Manual

Smart Machine Smart Decision
SIM7500A_User Manual_V1.00 2017-06-30
7
Figure Index
Figure 1: SIM7500 series Block Diagram .......................................................................................................... 10
Figure 2: Pin assignment overview .................................................................................................................... 12
Figure 3: Dimensions (Unit: mm) ...................................................................................................................... 16
Figure 4: Footprint recommendation (Unit: mm) ............................................................................................... 17
Figure 5: Power supply application circuit......................................................................................................... 18
Figure 6: Linear regulator reference circuit ....................................................................................................... 19
Figure 7: Switching modepower supply reference circuit .................................................................................. 19
Figure 8: ReferencePower on/offCircuit ............................................................................................................ 20
Figure 9: Power on timing sequence .................................................................................................................. 21
Figure 10: Power off timing sequence ............................................................................................................... 22
Figure 11: Reference reset circuit ...................................................................................................................... 23
Figure 12: UART full modem ............................................................................................................................ 24
Figure 13: UART null Modem ........................................................................................................................... 24
Figure 14: Reference circuit of level shift .......................................................................................................... 24
Figure 15: RI behaviour（SMS and URC report） ........................................................................................... 25
Figure 16: RI behaviour（voice call） .............................................................................................................. 25
Figure 17: USB reference circuit ....................................................................................................................... 26
Figure 18: USIM interface reference circuit ...................................................................................................... 27
Figure 19: Amphenol SIM card socket .............................................................................................................. 28
Figure 20: PCM_SYNC timing .......................................................................................................................... 29
Figure 21: EXT codec to module timing ............................................................................................................ 29
Figure 22: Module to EXT codec timing ........................................................................................................... 30
Figure 23: Audio codec reference circuit ........................................................................................................... 31
Figure 24: I2C reference circuit ......................................................................................................................... 31
Figure 25: NETLIGHT reference circuit ............................................................................................................ 32
Figure 26: ISINK reference circuit .................................................................................................................... 33
Figure 27: Antenna matching circuit (MAIN_ANT) .......................................................................................... 36
Figure 28: Antenna matching circuit (DIV_ANT) ............................................................................................. 36
Figure 31: Top and bottom view of Module ....................................................................................................... 44
Figure 32: Label Information ............................................................................................................................. 44
Figure 33: The ramp-soak-spike Reflow Profile of Module............................................................................... 45
Figure 34: Packaging introduce ......................................................................................................................... 47
Figure 35: Module tray drawing introduce......................................................................................................... 47
Figure 36: Small carton drawing introduce ........................................................................................................ 48
Figure 37: Big carton drawing introduce ........................................................................................................... 48
Figure 38: Reference design .............................................................................................................................. 49