Data Sheet

Table Of Contents

EMC3380 Series Wireless Module Data Manual

System memory Space

The EMC338x module contains the following memory cells:

KM4 Embedded SRAM

The KM4 core contains up to 512K bytes of continuous on-chip SRAM memory. The embedded SRAM is

available in bytes (8 bits), half words (16 bits) or single words (32 bits). It is divided into two blocks, both

of which can be accessed by the KM4 and KM0 cores.

⚫ KM4 SRAM1 (up to 256KB)

⚫ KM4 SRAM2 (up to 256KB)

Dividing SRAM into two sending device ports allows users' applications to obtain better

performance. For example, it is possible to access the SRAM through the CPU and the DMA controller

simultaneously without causing delay. Generally, when the DMA is reading and writing data from the

peripheral to the SRAM, the CPU will also access the SRAM to read and write the data of other peripherals.

Therefore, the reading and writing of different peripheral data is placed in different SRAM blocks Can

reduce latency. In addition, SRAM is read and written alternately to access the same peripheral data

sequence. For example, when the DMA is reading or writing to a RAM buffer and is ready to operate on

the next buffer, the CPU is notified. In this way, the CPU and DMA can operate different buffers in

different SRAM blocks at the same time, reducing access latency.

In the power supply area, the entire SRAM is also divided into 3 blocks:

⚫ SRAM_PD1 (up to 256KB)

⚫ SRAM_PD2 (up to 128KB)

⚫ SRAM_PD3 (up to 128KB)

Each block can be individually enabled in the power management unit (PMU), and this SRAM can be

restored as quickly as possible when the system wakes up from sleep mode.

KM0 Embedded SRAM

The KM0 core contains up to 64K bytes of memory. The embedded SRAM is available in bytes (8

bits), half words (16 bits) or single words (32 bits) and accessible by KM4 and KM0 cores.

KM4 Extension SRAM

If Bluetooth is not used, the KM4 core can be expanded with an additional 64KB of SRAM. This SRAM

can also be accessed through KM4 and KM0 at speeds up to 50MHz * 32 bits.

Retention SRAM

The chip also provides 1KB of SRAM, which is used to save data with the lowest power consumption

in deepsleep mode. This SRAM can also be accessed by KM4 and KM0.