Data Sheet
Table Of Contents
- Abstract
- 1. Introduction
- 2. Characteristics
- 3. Pin Definition
- 4. System memory Space
- 5. ATE（RF Test Mode）
- 5.1. Wi-Fi ATE Command
- 5.1.1. Start MP mode
- 5.1.2. Stop MP mode
- 5.1.3. Set Tx rate
- 5.1.4. Set operational channel
- 5.1.5. Set operational bandwidth
- 5.1.6. Set Tx power
- 5.1.7. Set antenna for Tx
- 5.1.8. Set antenna for Rx
- 5.1.9. Start air Rx mode
- 5.1.10. Start continuous Tx mode
- 5.1.11. Query air Rx statistics
- 5.1.12. Reset air Tx/Rx statistics
- 5.2. Bluetooth ATE Command（TBD）
- 5.3. Example Command
- 5.1. Wi-Fi ATE Command
- 6. Flash Programming
- 7. Electrical Parameters
- 8. RF Parameter
- 9. Antenna Information
- 10. Dimensions and Production Guidance
- 11. Production Guidelines
- 12. FCC and IC Information
- 12.1. FCC Warning
- 12.2. IC warning
- 12.3. Trace antenna designs
- 12.4. RF exposure considerations
- 12.5. Antennas
- 12.6. Label and compliance information
- 12.7. Information on test modes and additional testing requirements5
- 12.8. Additional testing, Part 15 Subpart B disclaimer
- 12.9. The module is limited to OEM installation ONLY.
- 12.10. The OEM integrator is responsible for ensuring that the end-user has no manual instructions to remove or install module.
- 12.11. The module is limited to installation in mobile or fixed applications
- 13. Packaging and Label Information
- 14. Sales and Technical Support Information
EMC3380 Series Wireless Module Data Manual
Copyright of Shanghai MXCHIP Information Technology Co., Ltd.
8
Characteristics
System and Storage
Processor
▪ Dual-core processor
▪ KM4: Use ARM latest v8M architecture, compatible with Cortex-M4F instruction set
▪ KM4: Use ARM latest v8M architecture, compatible with Cortex-M0 instruction set
▪ Two cores have equal access to SRAM, peripherals and registers
▪ Internal communication between the two processors
KM4 processor
▪ Compatible with Cortex-M4F instruction set, support FPU, DSP, MPU and TrustZone-M technologies
▪ Working frequency up to 200MHz (configurable)
▪ SWD serial debugging interface, support 8 hardware breakpoints and 4 observation points (SWO interface
function is not supported)
▪ Built-in NVIC interrupt vector table
▪ System tick timer.
▪ 32KB I-Cache and 4KB D-Cache.
K04 processor
Compatible with Cortex-M0 instruction set
Working frequency up to 20MHz
▪ Built-in NVIC interrupt vector table
▪ SWD serial debugging interface, support 4 hardware breakpoints and 2 observation points (SWO interface
function is not supported)
▪ System tick timer.
▪ 32KB I-Cache and 4KB D-Cache
KM4 CPU On-Chip memory
▪ Up to 512KB continuous space main SRAM, frequency up to 200MHz
▪ Up to 4MB PSRAM, frequency up to 50MHz
KM4 CPU On-Chip memory
▪ Up to 64KB of continuous space main SRAM, frequency up to 64MHz
▪ Reserve 1KB SRAM for saving data in low power mode
GDMA
▪ KM4 and KM0 both include a GDMA controller.
▪ HS-GDMA0 supports 6 channels and supports TrustZone-M technology