Data Sheet
Table Of Contents
- Abstract
- 1. Introduction
- 2. Characteristic
- 3. Pin Definition
- 4. System memory space
- 5. ATE（RF Test Mode）
- 5.1. ATE Command
- 5.1.1. Start MP mode
- 5.1.2. Stop MP mode
- 5.1.3. Set Tx rate
- 5.1.4. Set operational channel
- 5.1.5. Set operational bandwidth
- 5.1.6. Set Tx power
- 5.1.7. Set antenna for Tx
- 5.1.8. Set antenna for Rx
- 5.1.9. Start air Rx mode
- 5.1.10. Start continuous Tx mode
- 5.1.11. Query air Rx statistics
- 5.1.12. Reset air Tx/Rx statistics
- 5.2. Example Command
- 5.1. ATE Command
- 6. Flash Programing
- 7. Electrical parameters
- 8. Antenna Information
- 9. Assembly size and PCB package
- 10. Production Guidelines
- 11. FCC and IC Information
- 11.1. FCC Warning
- 11.2. IC warning
- 11.3. Trace antenna designs
- 11.4. RF exposure considerations
- 11.5. Antennas
- 11.6. Label and compliance information
- 11.7. Information on test modes and additional testing requirements5
- 11.8. Additional testing, Part 15 Subpart B disclaimer
- 11.9. The module is limited to OEM installation ONLY.
- 11.10. The OEM integrator is responsible for ensuring that the end-user has no manual instructions to remove or install module.
- 11.11. The module is limited to installation in mobile or fixed applications
- 12. Package and Label
- Appendix 1: Sales and Technical Support Information
EMC328x Series Wireless Module Data Manual
Copyright of Shanghai MXCHIP Information Technology Co., Ltd.
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System memory space
The EMC328x module contains the following memory units:：
KM4 Embedded SRAM
The KM4 core contains up to 512K bytes of continuous on-chip SRAM memory. The embedded SRAM
can pass byte (8 bits), halfword (16 bits) or single word (32 bits). It is divided into two blocks, which are
accessible by the KM4 and KM0 cores.
⚫ KM4 SRAM1 (up to 256KB)
⚫ KM4 SRAM2 (up to 256KB)
Dividing the SRAM into two delivery device ports allows the user's application to achieve better
performance. For example, SRAM can be accessed by both the CPU and the DMA controller without
causing delays. Generally speaking, when the DMA is reading and writing data from the peripheral to
the SRAM, the CPU also accesses the SRAM to read and write data of other peripherals. Therefore, the
read and write of different peripheral data are placed in different SRAM blocks. Can reduce the delay. In
addition, the SRAM is read and written alternately to access the same peripheral data sequence. For
example, the CPU is notified when the DMA is reading and writing to the RAM buffer and is ready to
operate on the next buffer. In this way, the CPU and DMA can simultaneously operate different buffers
in different SRAM blocks, reducing the delay of access.
In the power supply area, the entire SRAM is also divided into 3 blocks:
⚫ SRAM_PD1 (up to 256KB)
⚫ SRAM_PD2 (up to 128KB)
⚫ SRAM_PD3 (up to 128KB)
Each block can be individually set to open in the Power Management Unit (PMU), and this SRAM can be
recovered as quickly as the system wakes up from sleep mode.
KM0 Embedded SRAM
The KM0 core contains up to 64K bytes of memory. The embedded SRAM can pass byte (8 bits), halfword
(16 bits) or single word (32 bits). Can be accessed by the KM4 and KM0 cores.
KM4 Extension SRAM
f you don't use Bluetooth, the KM4 core can scale an extra 64KB of SRAM. The SRAM can also be accessed
by KM4 and KM0 at speeds up to 50MHz*32 bits.
Retention SRAM
The chip also provides 1KB of SRAM for saving data in the deep sleep mode with the lowest power
consumption. This SRAM can also be accessed by KM4 and KM0.