Data Sheet

Table Of Contents
EMC328x Series Wireless Module Data Manual
Copyright of Shanghai MXCHIP Information Technology Co., Ltd.
3
Characteristic
System and storage
Processor
Dual Core Processor
KM4: Adopt ARM's latest v8M architecture, compatible with Cortex-M4F instruction set
KM4: Adopt ARM's latest v8M architecture, compatible with Cortex-M0 instruction set
Two cores have equal access to SRAM, peripherals and registers
Internal communication between two processors
KM4 Processor
Compatible with Cortex-M4F instruction set, supporting FPU, DSP, MPU and TrustZone-M
technology
Operating frequency up to 200MHz (configurable)
SWD serial debugging interface, support 8 hardware breakpoints and 4 observation points (SWO
interface function is not supported)
Built-in NVIC interrupt vector table
System timer System tick timer.
32KB I-Cache and 4KB D-Cache.
K04 Processor
Compatible with Cortex-M0 instruction set
Operating frequency up to 20MHz
Built-in NVIC interrupt vector table
SWD serial debugging interface, supporting 4 hardware breakpoints and 2 observation points
(SWO interface function is not supported)
System timer System tick timer.
32KB I-Cache and 4KB D-Cache
KM4 CPU On-Chip memory
Up to 512KB of continuous space main SRAM with a frequency of 200MHz
(Specific models) can choose up to 4MB PSRAM, frequency up to 50MHz50MHz, 8bit DDR
(specific models)
KM4 CPU On-Chip memory
Up to 64KB continuous space main SRAM with a frequency of 64MHz
Reserve 1KB SRAM for saving data in low power mode
GDMA
KM4 and KM0 both contain a GDMA controller.