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Table Of Contents
Ehong
®
Professional Bluetooth Solutions Provider page 12 of 18
Figure 8：SPI timing diagram, one byte transmission, SPI mode
Symbol
Description
Note
Min.
Typ.
Max.
Units
Test
level
t
DC
Data to SCK setup.
10
ns
1
t
DH
SCK to data hold.
10
ns
1
t
CD
SCK to data valid.
C
LOAD
= 10 pF
97
2
ns
1
t
CL
SCK low time.
40
ns
1
t
CH
SCK high time.
40
ns
1
f
SCK
SCK frequency.
0.125
MHz
1
t
R
,
t
F
SCK rise and fall time.
ns
1
Figure 9： SPI timing parameters
6.8. SPI Debug
The two pin Serial Wire Debug (SWD) interface provided as a part of the Debug Access Port
(DAP) offers a flexible and powerful mechanism for non-intrusive debugging of program code.
Breakpoints and single stepping are part of this support.