CC1000 CC1000 Single Chip Very Low Power RF Transceiver Applications • Very low power UHF wireless data transmitters and receivers • 315 / 433 / 868 and 915 MHz ISM/SRD band systems • RKE – Two-way Remote Keyless Entry • • • • • Home automation Wireless alarm and security systems AMR – Automatic Meter Reading Low power telemetry Game Controllers and advanced toys Product Description CC1000 is a true single-chip UHF trans- CC1000 is based on Chipcon’s SmartRF® ceiver designed for very low power and very
CC1000 Table of Contents CC1000........................................................................................................................... 1 Single Chip Very Low Power RF Transceiver........................................................... 1 1. Absolute Maximum Ratings ................................................................................... 4 2. Operating Conditions ............................................................................................. 4 3.
CC1000 20. Input / Output Matching...................................................................................... 31 21. Output power programming .............................................................................. 32 22. RSSI output ......................................................................................................... 33 23. IF output .............................................................................................................. 34 24. Crystal oscillator..
CC1000 1. Absolute Maximum Ratings Parameter Min. Max. Units -0.3 -0.3 5.0 VDD+0.3, max 5.
CC1000 Parameter Output power 433 MHz 868 MHz Min. Typ. Max. Unit Condition / Note 10 5 dBm dBm Delivered to 50 Ω load. The output power is programmable. -20 -20 140 / 80 Ω Transmit mode. For matching details see “Input/ output matching” p.31. -20 dBc An external LC or SAW filter should be used to reduce harmonics emission to comply with SRD requirements. See p.36. Receiver Sensitivity, 433 MHz Optimum sensitivity (9.3 mA) Low current consumption (7.4 mA) -110 -109 dBm dBm 2.
CC1000 Parameter Min. Typ. Max. Unit Condition / Note 16 MHz Crystal frequency can be 3-4, 6-8 or 9-16 MHz. Recommended frequencies are 3.6864, 7.3728, 11.0592 and 14.7456. See page 35 for details. ppm 433 MHz 868 MHz The crystal frequency accuracy and drift (ageing and temperature dependency) will determine the frequency accuracy of the transmitted signal.
CC1000 Parameter Min. Typ. Max. Unit Current Consumption, receive mode 433/868 MHz 7.4/9.6 mA Current Consumption, average in receive mode using polling 433/868 MHz 74/96 µA P=0.01mW (-20 dBm) 5.3/8.6 mA P=0.3 mW (-5 dBm) 8.9/13.8 mA P=1 mW (0 dBm) 10.4/16.5 mA P=3 mW (5 dBm) 14.8/25.4 mA P=10 mW (10 dBm) 26.7/NA mA Current Consumption, crystal osc. 30 80 105 µA µA µA Current Consumption, crystal osc. And bias 860 µA Current Consumption, crystal osc.
CC1000 4. Pin Assignment Pin no. 1 2 3 4 5 6 7 8 9 10 11 12 UltraCSP pin no.
CC1000 5. Circuit Description RSSI/IF MIXER RF_IN LNA DEMOD IF STAGE CONTROL DIO 3 DCLK PDATA, PCLK, PALE /N RF_OUT PA BIAS VCO ~ L1 L2 CHARGE PUMP LPF R_BIAS XOSC_Q2 PD /R OSC XOSC_Q1 CHP_OUT Figure 1. Simplified block diagram of the CC1000 A simplified block diagram of CC1000 is shown in Figure 1. Only signal pins are shown. In receive mode CC1000 is configured as a traditional superheterodyne receiver.
CC1000 6. Application Circuit Very few external components are required for the operation of CC1000. A typical application circuit is shown in Figure 2. Component values are shown in Table 1. 6.1 Input / output matching C31/L32 is the input match for the receiver. L32 is also a DC choke for biasing. C41, L41 and C42 are used to match the transmitter to 50 Ω. An internal T/R switch circuit makes it possible to connect the input and output together and match the CC1000 to 50 Ω in both RX and TX mode.
CC1000 CC1000 TSSOP package Item C31 C41 C42 C171 C181 L32 L41 L101 R131 XTAL 315 MHz 8.2 pF, 5%, C0G, 0603 2.2 pF, 5%, C0G, 0603 5.6 pF, 5%, C0G, 0603 18 pF, 5%, C0G, 0603 18 pF, 5%, C0G, 0603 39 nH, 10%, 0805 433 MHz 15 pF, 5%, C0G, 0603 8.2 pF, 5%, C0G, 0603 5.6 pF, 5%, C0G, 0603 18 pF, 5%, C0G, 0603 18 pF, 5%, C0G, 0603 68 nH, 10%, 0805 868 MHz 10 pF, 5%, C0G, 0603 Not used 4.7 pF, 5%, C0G, 0603 18 pF, 5%, C0G, 0603 18 pF, 5%, C0G, 0603 120 nH, 10%, 0805 915 MHz 10 pF, 5%, C0G, 0603 Not used 4.
CC1000 7. Configuration Overview CC1000 can be configured to achieve the best performance for different applications.
CC1000 9. 3-wire Serial Configuration Interface CC1000 is configured via a simple 3-wire The timing for the programming is also shown in Figure 4 with reference to Table 2. The clocking of the data on PDATA is done on the negative edge of PCLK. When the last bit, D0, of the 8 data-bits has been loaded, the data word is loaded in the internal configuration register. interface (PDATA, PCLK and PALE). There are 28 8-bit configuration registers, each addressed by a 7-bit address.
CC1000 PCLK Address PDATA 6 5 4 3 Read mode 2 1 0 R Data byte 7 6 5 4 3 2 1 0 PALE Figure 5. Configuration registers read operation Parameter Symbol Min Max Units Conditions PCLK, clock frequency FCLOCK - 10 MHz PCLK low pulse duration TCL,min 50 ns The minimum time PCLK must be low. PCLK high pulse duration TCH,min 50 ns The minimum time PCLK must be high. PALE setup time TSA 10 - ns The minimum time PALE must be low before negative edge of PCLK.
CC1000 10. Microcontroller Interface Used in a typical system, CC1000 will interface to a microcontroller. This microcontroller must be able to: • • Program CC1000 into different modes via the 3-wire serial configuration interface (PDATA, PCLK and PALE). Interface to the bi-directional synchronous data signal interface (DIO and DCLK). 10.1 Connecting the microcontroller The microcontroller uses 3 output pins for the configuration interface (PDATA, PCLK and PALE).
CC1000 11. Signal interface The signal interface consists of DIO and DCLK and is used for the data to be transmitted and data received. DIO is the bi-directional data line and DCLK provides a synchronous clock both during data transmission and data reception. is presented at DIO. The data should be clocked into the interfacing circuit at the rising edge of DCLK. See Figure 8. The CC1000 can be used with NRZ (NonReturn-to-Zero) data or Manchester (also known as bi-phase-level) encoded data.
CC1000 Transmitter side: DIO Data provided by microcontroller DCLK Clock provided by CC1000 “RF” FSK modulating signal (NRZ), internal in CC1000 Receiver side: “RF” Demodulated signal (NRZ), internal in CC1000 DCLK Clock provided by CC1000 DIO Data provided by CC1000 Figure 7.
CC1000 Transmitter side: DIO Data provided by UART (TXD) DCLK DCLK is not used in transmit mode. Used as data output in receive mode. “RF” FSK modulating signal, internal in CC1000 Receiver side: “RF” Demodulated signal, internal in CC1000 DIO DIO is not used in receive mode. Used only as data input in transmit mode. DCLK Data output provided by CC1000. Connect to UART (RXD). Figure 9. Transparent Asynchronous UART mode 10110001101 TX data Time Figure 10.
CC1000 12. Bit synchroniser and data decision Average filter Sampler Frequency detector Data filter Decimator Data slicer comparator Figure 11. Demodulator block diagram A block diagram of the digital demodulator is shown in Figure 11. The IF signal is sampled and its instantaneous frequency is detected. The result is decimated and filtered. In the data slicer the data filter output is compared to the average filter output to generate the data output.
CC1000 Settling NRZ mode MODEM1. SETTLING (1:0) 00 01 10 11 Manual Lock UART mode MODEM1.LOCK_ AVG_MODE=’1’ MODEM1.LOCK_ AVG_IN=’0’=→’1’** NRZ mode MODEM1.LOCK_ AVG_MODE=’1’ MODEM1.LOCK_ AVG_IN=’0’=→’1’** 14 25 46 89 Automatic Lock UART mode MODEM1.LOCK_ AVG_MODE=’0’ MODEM1.LOCK_ AVG_IN=’X’*** 11 22 43 86 16 32 64 128 MODEM1.LOCK_ AVG_MODE=’0’ MODEM1.LOCK_ AVG_IN=’X’*** 16 32 64 128 Notes: ** The averaging filter is locked when MODEM1.LOCK_AVG_IN is set to 1 *** X = Do not care.
CC1000 Data package to be received Noise RX Preamble PD NRZ data Noise RX Averaging filter locked Averaging filter free-running / not used Automatically locked after a short period depending on “SETTLING” Figure 12. Automatic locking of the averaging filter Data package to be received Noise PD Preamble NRZ data Noise RX Averaging filter locked Averaging filter free-running Manually locked after preamble is detected Figure 13.
CC1000 13. Receiver sensitivity versus data rate and frequency separation The receiver sensitivity depends on the data rate, the data format, FSK frequency separation and the RF frequency. Typical figures for the receiver sensitivity (BER = 10-3) are shown in Table 6 for 64 kHz frequency separations and Table 7 for 20 kHz separations. Optimised sensitivity Data rate [kBaud] 0.6 1.2 2.4 4.8 9.6 19.2 38.4 76.
CC1000 14. Frequency programming RX mode: fRF (Receive frequency) fLO (low-side) fLO (high-side) fIF fvco fIF TX mode: f0 (Lower FSK frequency) f1 (Upper FSK frequency) fRF (Center frequency) fvco fsep Figure 15. Relation between fvco, fif, and LO frequency The frequency synthesiser (PLL) is controlled by the frequency word in the configuration registers. There are two frequency words, A and B, which can be programmed to two different frequencies.
CC1000 synthesis PLL is near the limit of generate the frequency requested, and the PLL should be recalibrated. It is recommended that the LOCK_CONTINOUS bit in the LOCK register is checked when changing frequencies and when changing between RX and TX mode. If lock is not achieved, a calibration should be performed. 15. Recommended RX settings for ISM frequencies Shown in Table 9 are the recommended RX frequency synthesiser settings for a few operating frequencies in the popular ISM bands.
CC1000 16. VCO Only one external inductor (L101) is required for the VCO. The inductor will determine the operating frequency range of the circuit. It is important to place the inductor as close to the pins as possible in order to reduce stray inductance. It is recommended to use a high Q, low tolerance inductor for best performance. Typical tuning range for the integrated varactor is 20-25%. Component values for various frequencies are given in Table 1.
CC1000 Start single calibration Write FREQ_A, FREQ_B If DR>=9.
CC1000 Start dual calibration Write FREQ_A, FREQ_B If DR>=38kBd then write TEST4: L2KIO=3Fh Write CAL: CAL_DUAL = 1 Write MAIN: RXTX = 0; F_REG = 0 RX_PD = 0; TX_PD = 1; FS_PD = 0 CORE_PD = 0; BIAS_PD = 0; RESET_N=1 Write CURRENT= RX current Write PLL= RX pll Write CAL: CAL_START=1 Wait for maximum 34 ms, or Read CAL and wait until CAL_COMPLETE=1 Frequency registers A and B are both used for RX mode Either frequency register A or B is selected Update CURRENT and PLL for RX mode Dual calibration is
CC1000 18. VCO and LNA current control The VCO current is programmable and should be set according to operating frequency RX/TX mode and output power. Recommended settings for the VCO_CURRENT bits in the CURRENT register are shown in the tables on page 41. RF frequency [MHz] Current consumption [mA] The bias current for the LNA, and the LO and PA buffers are also programmable. Table 10 shows the current consumption and receiver sensitivity for different settings (2.4 kBaud Manchester encoded data).
CC1000 Power Off Power turned on Initialise and reset CC1000 MAIN: RXTX = 0 F_REG = 0 RX_PD = 1 TX_PD = 1 FS_PD = 1 CORE_PD = 0 BIAS_PD = 1 RESET_N = 0 MAIN: RESET_N = 1 Wait 2 ms* Program all registers except MAIN Calibrate VCO and PLL Reset and turning on the crystal oscillator core *Time to wait depends on the crystal frequency and the load capacitance Frequency register A is used for RX mode, register B for TX Calibration is performed according to single calibration algorithm for both RX and TX mo
CC1000 Power Down Turn on crystal oscillator core MAIN: CORE_PD = 0 Wait 2 ms* *Time to wait depends on the crystal frequency and the load capacitance Turn on bias generator BIAS_PD = 0 Wait 200 µs RX Turn on RX: MAIN: RXTX = 0, F_REG = 0 RX_PD = 0, FS_PD = 0 CURRENT = ‘RX current’ PLL = ’RX pll’ Wait 250 µs RX mode RX or TX? TX Turn on TX: PA_POW = 00h MAIN: RXTX = 1, F_REG = 1 TX_PD = 0, FS_PD = 0 CURRENT = ‘TX current’ PLL = ’RX pll’ Wait 250 µs PA_POW = ‘Output power’ Wait 20 µs Turn off RX:
CC1000 20. Input / Output Matching A few passive external components combined with the internal T/R switch circuitry ensures match in both RX and TX mode. The matching network is shown in Figure 20. Component values for various frequencies are given in Table 1. Component values for other frequencies can be found using the configuration software. C31 RF_IN TO ANTENNA RF_OUT CC1000 C42 C41 L41 L32 AVDD=3V Figure 20.
CC1000 21. Output power programming The RF output power is programmable and controlled by the PA_POW register. Table 11 shows the closest programmable value for output powers in steps of 1 dB. The typical current consumption is also shown. Output power [dBm] -20 -19 -18 -17 -16 -15 -14 -13 -12 -11 -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 7 8 9 10 In power down mode the PA_POW should be set to 00h for minimum leakage current. RF frequency 433 MHz PA_POW Current consumption, [hex] typ. [mA] 01 6.
CC1000 22. RSSI output CC1000 has a built-in RSSI (Received Signal Strength Indicator) giving an analogue output signal at the RSSI/IF pin. The IF_RSSI bits in the FRONT_END register enable the RSSI. When the RSSI function is enabled, the output current of this pin is inversely proportional to the input signal level. The output should be terminated in a resistor to convert the current output into a voltage. A capacitor is used in order to low-pass filter the signal.
CC1000 23. IF output CC1000 has a built-in 10.7 MHz IF output buffer. This buffer could be applied in narrowband applications with requirements on mirror image filtering. The system is then built with CC1000, a 10.7 MHz ceramic filter and an external 10.7 MHz demodulator. The external network for IF output operation is shown in Figure 23. R281 = 470 Ω, C281 = 3.3nF. CC1000 The external network provides 330 Ω source impedance for the 10.7 MHz ceramic filter. RSSI/IF To 10.
CC1000 24. Crystal oscillator CC1000 has an advanced amplitude regulated crystal oscillator. A high current is used to start up the oscillations. When the amplitude builds up, the current is reduced to what is necessary to maintain a 600 mVpp amplitude. This ensures a fast start-up, keeps the current consumption as well as the drive level to a minimum and makes the oscillator insensitive to ESR variations. Using the internal crystal oscillator, the crystal must be connected between XOSC_Q1 and XOSC_Q2.
CC1000 25. Optional LC Filter An optional LC filter may be added between the antenna and the matching network in certain applications. The filter will reduce the emission of harmonics and increase the receiver selectivity. The filter topology is shown in Figure 25. Component values are given in Table 13. The filter is designed for 50 Ω terminations. The component values may have to be tuned to compensate for layout parasitics. L71 C71 C72 Figure 25.
CC1000 26. System Considerations and Guidelines 26.1 SRD regulations International regulations and national laws regulate the use of radio receivers and transmitters. SRDs (Short Range Devices) for licence free operation are allowed to operate in the 433 and 868-870 MHz bands in most European countries. In the United States such devices operate in the 260–470 and 902-928 MHz bands. CC1000 is designed to meet the requirements for operation in all these bands.
CC1000 27. PCB Layout Recommendations Chipcon provide reference layouts that should be followed in order to achieve the best performance. The Chipcon reference design (CC1000PP and CC1000uCSP_EM) can be downloaded from the Chipcon website. A two layer PCB is highly recommended. The bottom layer of the PCB should be the “ground-layer”. The top layer should be used for signal routing, and the open areas should be filled with etallization connected to ground using several vias.
CC1000 29. Configuration registers The configuration of CC1000 is done by programming 22 8-bit configuration registers. The configuration data based on selected system parameters are most easily found by using the SmartRF® Studio software. A complete description of the registers are given in the following tables. After a RESET is programmed all the registers have default values.
CC1000 MAIN Register (00h) REGISTER NAME MAIN[7] MAIN[6] RXTX F_REG Default value - MAIN[5] RX_PD - H MAIN[4] MAIN[3] MAIN[2] MAIN[1] TX_PD FS_PD CORE_PD BIAS_PD - H H H H MAIN[0] RESET_N - L FREQ_2A Register (01h) REGISTER NAME FREQ_2A[7:0] FREQ_A[23:16] FREQ_1A Register (02h) REGISTER NAME FREQ_1A[7:0] FREQ_A[15:8] FREQ_0A Register (03h) REGISTER NAME FREQ_0A[7:0] FREQ_A[7:0] FREQ_2B Register (04h) REGISTER NAME FREQ_2B[7:0] FREQ_B[23:16] FREQ_1B Register (05h) REGISTER NAME FREQ_1B
CC1000 CURRENT Register (09h) REGISTER NAME CURRENT[7:4] VCO_CURRENT[3:0] Default value 1100 Active - Description Control of current in VCO core for TX and RX 0000 : 150µA 0001 : 250µA 0010 : 350µA 0011 : 450µA 0100 : 950µA, use for RX, f= 400 – 500 MHz 0101 : 1050µA 0110 : 1150µA 0111 : 1250µA 1000 : 1450µA, use for RX, f<400 MHz and f>500 MHz; and TX, f= 400 – 500 MHz 1001 : 1550µA, use for TX, f<400 MHz 1010 : 1650µA 1011 : 1750µA 1100 : 2250µA 1101 : 2350µA 1110 : 2450µA 1111 : 2550µA, use for TX, f
CC1000 PA_POW Register (0Bh) REGISTER PA_POW[7:4] PA_HIGHPOWER[3:0] Default value 0000 PA_POW[3:0] PA_LOWPOWER[3:0] 1111 - NAME Default value Active EXT_FILTER 0 - PLL Register (0Ch) REGISTER PLL[7] PLL[6:3] NAME REFDIV[3:0] 0010 Active - - Description Control of output power in high power array. Should be 0000 in PD mode . See Table 11 page 32 for details. Control of output power in low power array Should be 0000 in PD mode. See Table 11 page 32 for details.
CC1000 LOCK Register (0Dh) REGISTE NAME R LOCK[7:4] LOCK_SELECT[3:0] Default value 0000 Active - Description Selection of signals to CHP_OUT (LOCK) pin 0000 : Normal, pin can be used as CHP_OUT 0001 : LOCK_CONTINUOUS (active high) 0010 : LOCK_INSTANT (active high) 0011 : ALARM_H (active high) 0100 : ALARM_L (active high) 0101 : CAL_COMPLETE (active high) 0110 : IF_OUT 0111 : REFERENCE_DIVIDER Output 1000 : TX_PDB (active high, activates external PA when TX_PD=0) 1001 : Manchester Violation (active high)
CC1000 MODEM2 Register (0Fh) REGISTER NAME MODEM2[7] PEAKDETECT Default value 1 MODEM2[6:0] PEAK_LEVEL_OFFSET[6:0] 0010110 Note: PEAK_LEVEL_OFFSET[6:0] = Fs Fs − IFlow IF + ∆f low ⋅ 2 5 8 where Fs = Active - H Description Peak Detector and Remover disabled or enabled 0 : Peak detector and remover is disabled 1 : Peak detector and remover is enabled Threshold level for Peak Remover in Demodulator. Correlated to frequency deviation, see note.
CC1000 MODEM0 Register (11h) REGISTER NAME MODEM0[7] MODEM0[6:4] BAUDRATE[2:0] Default value 010 MODEM0[3:2] DATA_FORMAT[1:0] 01 - MODEM0[1:0] XOSC_FREQ[1:0] 00 - MATCH Register (12h) REGISTER NAME MATCH[7:4] RX_MATCH[3:0] MATCH[3:0] TX_MATCH[3:0] 0000 FSCTRL[7:4] FSCTRL[3:1] FSCTRL[0] Description - Default value 0000 FSCTRL Register (13h) REGISTER NAME Active Not used 000 : 0.6 kBaud 001 : 1.2 kBaud 010 : 2.4 kBaud 011 : 4.8 kBaud 100 : 9.6 kBaud 101 : 19.2, 38.4 and 76.
CC1000 PRESCALER Register (1Ch) REGISTER NAME PRESCALER[7:6] PRESCALER[5:4] PRE_SWING[1:0] PRE_CURRENT [1:0] Default value 00 Active 00 - Prescaler swing.
CC1000 TEST3 Register (for test only, 43h) REGISTER NAME TEST3[7:5] TEST3[4] BREAK_LOOP Default value 0 TEST3[3:0] CAL_DAC_OPEN 0100 - Default value - Active Default value - Active Default value - Active TEST2 Register (for test only, 44h) REGISTER NAME TEST2[7:5] TEST2[4:0] CHP_CURRENT [4:0] TEST1 Register (for test only, 45h) REGISTER NAME TEST1[7:4] TEST1[3:0] CAL_DAC[3:0] TEST0 Register (for test only, 46h) REGISTER NAME TEST0[7:4] TEST0[3:0] VCO_ARRAY[3:0] SWRS048A Active - - - -
CC1000 30. Package Description (TSSOP-28) Note: The figure is an illustration only. TSSOP 28 Min Max All dimensions in mm Thin Shrink Small Outline Package (TSSOP) D E1 E A A1 e B 9.60 4.30 0.05 0.19 6.40 0.65 9.80 4.50 1.20 0.15 0.30 SWRS048A L 0.45 Copl. α 0° 0.75 0.
CC1000 31. Package Description (UltraCSP™) Top view A1 A2 A3 A4 B1 B2 B3 B4 2339um +/- 20um C1 C2 C3 C4 D1 D2 D3 D4 4034um +/- 20um E1 E2 E3 E4 F1 F2 F3 F4 500um +/- 10um G1 G4 G3 G2 535um +/-20um 392um +/-20um 292um +/-20um 250um +/- 10um 500um +/- 10um 417um +/-20um Bump pitch is 500um centre to centre in both directions.
CC1000 Vertical cross section (UltraCSP™) Before assembly on PCB: Die A h1 Solder bumps (Pb free) After assembly on PCB: A Die h2 PCB mounting pads Die thickness (A) 432um Bump height before assembly (h1) 200um +/- 20um Bump height after assembly (h2) 140um +/- tbd um Total height before assembly 632um +/- 20um Total height after assembly 572um +/- tbd um Table 14: Height budget SWRS048A Page 50 of 55
CC1000 32. Plastic Tube Specification TSSOP 4.4mm (.173”) antistatic tube. Package Tube Width TSSOP 28 268 mil Tube Specification Tube Height Tube Length 80 mil 20” Units per Tube 50 33. Waffle Pack Specification Package UltraCSP™ Waffle Pack Width 50.8 mm Waffle Pack Specification Waffle Pack Length Waffle Pack Length Units per Waffle Pack 50.8 mm 117 3.96 mm 34. Carrier Tape and Reel Specification Carrier tape and reel is in accordance with EIA Specification 481.
CC1000 35. Ordering Information Chipcon Part Number* CC1000-RTB1 TI Part Number Description CC1000PW CC1000-RTR1 CC1000PWR CC1000-RWP2 CC1000YZ Single Chip RF Transceiver. CC1000, TSSOP 28 package, RoHS compliant Pbfree assembly in tubes with 50 pcs per tube. Single Chip RF Transceiver. CC1000, TSSOP 28 package, RoHS compliant Pbfree assembly, T&R with 2500 pcs per reel. Single Chip RF Transceiver. CC1000, UltraCSP™ package, RoHS compliant Pbfree assembly with 117 pcs per waffle pack.
CC1000 Data Sheet Identification Product Status Definition Obsolete Not In Production This data sheet contains specifications on a product that has been discontinued by Chipcon. The data sheet is printed for reference information only.
CC1000 37. Address Information Texas Instruments Norway AS Gaustadalléen 21 N-0349 Oslo NORWAY Tel: +47 22 95 85 44 Fax: +47 22 95 85 46 Web site: http://www.ti.com/lpw 38. TI Worldwide Technical Support Internet TI Semiconductor Product Information Center Home Page: TI Semiconductor KnowledgeBase Home Page: support.ti.com support.ti.com/sc/knowledgebase 39. Product Information Centers Americas Phone: +1(972) 644-5580 Fax: +1(972) 927-6377 Internet/Email: support.ti.com/sc/pic/americas.
CC1000 Asia Phone International Domestic Australia China Hong Kong India Indonesia Korea Malaysia New Zealand Philippines Singapore Taiwan Thailand +886-2-23786800 Toll-Free Number 1-800-999-084 800-820-8682 800-96-5941 +91-80-51381665 (Toll) 001-803-8861-1006 080-551-2804 1-800-80-3973 0800-446-934 1-800-765-7404 800-886-1028 0800-006800 001-800-886-0010 Fax +886-2-2378-6808 Email tiasia@ti.com or ti-china@ti.com Internet support.ti.com/sc/pic/asia.
PACKAGE MATERIALS INFORMATION www.ti.com 4-Feb-2009 TAPE AND REEL INFORMATION *All dimensions are nominal Device CC1000PWR Package Package Pins Type Drawing TSSOP PW 28 SPQ Reel Reel Diameter Width (mm) W1 (mm) 2500 330.0 16.4 Pack Materials-Page 1 A0 (mm) B0 (mm) K0 (mm) P1 (mm) 6.8 10.2 1.6 8.0 W Pin1 (mm) Quadrant 16.
PACKAGE MATERIALS INFORMATION www.ti.com 4-Feb-2009 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CC1000PWR TSSOP PW 28 2500 378.0 70.0 346.
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