User`s guide

Setup Menus
45
Advanced Chipset Control Submenu
Table 3-12 lists the options in the advanced chipset control submenu.
Table 3-12 Advanced Chipset Control Submenu
Feature Option Description
Address Bit
Permuting
Disabled
Enabled
To be enabled, there must be a power of 2 number of
rows, all rows must be the same size, and all populated
rows must be adjacent and start at row 0. Two-way or
four-way permuting is set automatically based on
memory configuration.
Base RAM Step 1 MB
1 KB
Every location
Tests base memory once per MB, once per KB, or every
location.
Extended RAM
Step
1 MB
1 KB
Every location
Tests extended memory once per MB, once per KB, or
every location.
L2 Cache Enabled
Disabled
When enabled, the secondary cache is sized and
enabled.ForCoreClockFrequency-to-SystemBusratios
equal to two, BIOS automatically disables the L2 cache.
ISA Expansion
Aliasing
Enabled
Disabled
When enabled, every I/O access with an address in the
range x100-x3FFh, x500-x7FFh, x900-xBFF, and
xD00-xFFFh is internally aliased to the range
0100-03FFh before any other address range checking is
performed.
Memory
Scrubbing
Disabled
Enabled
When enabled, BIOS automatically detects and corrects
SBEs.
Restreaming
Buffer
Enabled
Disabled
When enabled, the data returned and buffered for a
Delayed Inbound Read can be reaccessed following a
disconnect.
ReadPrefetchfor
PXB0A
N/A Information field only. Configures the number of
Dwords that are prefetched on Memory Read Multiple
commands.
ReadPrefetchfor
PBX0B
N/A Information field only. Configures the number of
Dwords that are prefetched on Memory Read Multiple
commands.