Servosila-Device-Reference-0xA020192

this parameter helps correct the mismatch. 0x04,
rw
4
request
frequency:
divider
- The parameter defines how often the controller reads out data from the encoder.
Specifically, this parameters specifies how often pulse trains are sent by the
controller to the encoder via SCK line. This line is sometimes called SCLK or
CLOCK. Note that the encoder sends a single bit of data back to the controller
via MISO line each time it receives a pulse from the controller. By sending a
train of pulses, the controller reads out all the data bits (a packet) from the
encoder.
The parameter specifies a divider for the controller's sampling frequency.
For example:
The controller has a sampling frequency of 15 kHz or 15 000 samples per second
(check this for your controller in "Device Information" telemetry section). If the
divider is specified as 4, then the request frequency is 15 000 / 4 = 3750 Hz =
3.75kHz. This means that the controller reads out the data from the encoder 3750
times a second.
Note that the request frequency should be aligned with a maximum request
frequency specified in the encoder's datasheet.
UINT16,
0x3014,
0x10,
rw
5 clock
frequency:
divider
- This parameter characterizes pulses within a train of pulses that are sent by the
controller to the encoder via SCK line to read out a data packet. This line is
sometimes called SCLK or CLOCK. The pulses are generated by a silicon
peripheral that has peculiarities of configuration as explained below.
The parameter specifies a divider for CPU frequency of the controller. The
formula for the pulse's frequency is the following:
clock frequency = [Half of CPU frequency] / (divider + 1)
Example:
If the controller's CPU frequency is 90 MHz, and "clock frequency: divider" is
configured as 89, then this results in the following clock frequency: 90 MHz / 2 /
(89 + 1) = 45 Mhz / 90 = 500kHz.
Intuition for selecting the clock frequency:
• The clock frequency should not be higher than a maximum clock
frequency defined in the encoder's datasheet.
• On the other hand, the clock frequency should be high enough, so that the
entire pulse train fits in a time window between subsequent data reads.
Note that the frequency of data reads is defined by "request frequency:
divider" parameter.
UINT16,
0x3014,
0x11,
rw
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