Datasheet

Intel
®
Server Board S5000PAL/S5000XAL TPS Power and Environmental Specifications
Revision 2.0
Intel order number: D31979-011
63
8.2.8 Dynamic Loading
The output voltages shall remain within limits for the step loading and capacitive loading
specified in the table below.
The load transient repetition rate shall be tested between 50 Hz and
5 kHz at duty cycles ranging from 10%-90%.
The load transient repetition rate is only a test
specification.
The step load may occur anywhere within the MIN load to the MAX
load conditions.
Table 38. Transient Load Requirements
Output Step Load Size
(See note 2)
Load Slew Rate Test capacitive Load
+3.3V 5.0A
0.25 A/ sec 250 F
+5V 6.0A
0.25 A/ sec 400 F
12V1+12V2+12V3+12
V4
28.0A
0.25 A/ sec 2200 F
1,2
+5VSB 0.5A
0.25 A/ sec 20 F
Notes:
1) Step loads on each 12V output may happen simultaneously.
2) The +12V should be tested with 2200 F evenly split between the four +12V rails.
8.2.9 Capacitive Loading
The power supply shall be stable and meet all requirements with the following capacitive
loading ranges.
Table 39. Capacitive Loading Conditions
Output MIN MAX Units
+3.3V 250 6,800
F
+5V 400 4,700
F
+12V1,2,3,4 500 each 11,000
F
-12V 1 350
F
+5VSB 20 350
F
8.2.10 Closed-Loop Stability
The power supply shall be unconditionally stable under all line/load/transient load conditions
including capacitive load ranges.
A minimum of: 45 degrees phase margin and -10dB-gain
margin is required.
Closed-loop stability must be ensured at the maximum and minimum loads
as applicable.
8.2.11 Common Mode Noise
The common mode noise on any output shall not exceed 350 mV pk-pk over the frequency
band of 10Hz to 30MHz.
1. The measurement shall be made across a 100 Ω resistor between each of the DC
outputs, including ground, at the DC power connector and chassis ground (power
subsystem enclosure).
2. The test set-up shall use an FET probe such as Tektronix* model P6046 or equivalent.