Datasheet

Intel

Server Board S5000PAL/S5000XAL TPS Functional Architecture

Revision 2.0

Intel order number: D31979-011

3. Functional Architecture

The architecture and design of the Intel

Server Board S5000PAL/S5000XAL is based on the

Intel

5000 Chipset Family. The chipset is designed for systems based on the Dual-Core Intel

Xeon

processor 5000 sequence with system bus speeds of 667 MHz, 1066 MHz, and 1333

MHz. The chipset is made up of two main components: the Memory Controller Hub (MCH) for

the host bridge and the ESB-2 I/O controller hub for the I/O subsystem. This chapter provides a

high-level description of the functionality associated with each chipset component and the

architectural blocks that make up this server board. For more in depth detail of the functionality

for each of

the chipset components and each of the functional architecture blocks, see the Intel

S5000 Server Board Family Datasheet.

Figure 10. Server Board Functional Block Diagram

Note: The diagram above uses the Intel

5000P MCH as a general reference designator for

both MCH components supported on this server board.