User's Manual

PRELIMINARY DATA SHEET • SKY66430-11: LTE FOR IoT SYSTEM-in-PACKAGE
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • [e-mail] • www.skyworksinc.com
2 August 26, 2019 • Skyworks Proprietary and Confidential Information • Products and Product Information are Subject to Change Without Notice • 204412F
Transceiver Section
A direct-conversion RF solution using low power technology has
the following functional characteristics:
 Direct conversion in the Tx and Rx paths
 On-chip Fractional-N frequency synthesizers
 On-chip anti-alias filters
 On-chip AGC circuit
 On-chip reconstruction filters
 On-chip calibration including VCO and DC offset correction in
the Rx paths
 Rx and Tx gain and phase correction loops between the RF
and baseband
 Software control for synthesizer, Tx/Rx, adjustment, and gain
control
 External clock reference of 38.4 MHz
Baseband Modem Section
 DL processing block, handling LTE downlink physical layer
(Rx)
 UL processing block, handling LTE uplink physical layer (Tx)
 Synchronization processing block, handling frequency search
and synchronization to LTE network
 Optimized for new Cat-M1 channels and operation of 3GPP
Release 13
 An MCU with instruction and data cache, running LTE protocol
stack at frequency up to 312 MHz
 A quad-IO SPI interface (QSPI) to 1.8 V serial NOR flash of
64 Mbit or 128 Mbit size, running at 104 MHz, with support of
eXecute-in-Place (XIP) and critical word first wrapping reads
 A pSRAM controller interfacing with an embedded 64-Mbit
pSRAM at 104 MHz
 Three high-speed UARTs with hardware flow control
 One I
2
C master up to 3.4 Mbps
 One SPI master and slave up to 13 MHz
 Muxed GPIOs interruptible, with support of pulse counter and
PWM functionality
 Two UICC interfaces compliant with ETSI TS 102 221
specification, including SIM card removal detection and
support for 1.8 V and 3 V voltage levels
 Secured JTAG, with possibility of enabling or disabling the
interface by hardware or secured software
NOTE: This SiP includes the Sequans Monarch 3330 chipset.
For more specific information related to that chipset,
which is not included in this data sheet, refer to the data
sheet for that product.
A functional block diagram is shown in Figure 1. A typical
application block diagram is shown in Figure 2. The pinout is
shown in Figure 3. Signal pin assignments and functional pin
descriptions are described in Table 1.