Data Sheet

PBA RF Module ATM210
5GHz
Wireless Audio Transceiver
REV: 00
T
Hd
Hold time 25 ns
T
Od
Output delay -25 25 ns
Bit clocks/Word clock 64
I2S protocol is “I2S Justified” as shown below.
*The timing specified for the rise and fall times represents the edge rates on the module itself. The rise and fall times
of the I2S signals are determined by ESD/EMI mitigation components on the modules, as well as external loading, and
will be higher than the specified numbers
5-10. I
2
C Slave Communication Interface Timing
The ATM210 has both I2C slave and master interfaces available with their respective pins S_SCL, S_SDA and
M_SCL, M_SDA. The interfaces operate in I2C fast-mode and can receive and transmit at up to 400 kbit/s.
Bytes are 8 bits long and are transferred with the most significant bit (MSB) first. Each byte has to be
followed by an acknowledge bit. The SWA52 will apply clock-stopping (by holding the clock line S_SCL LOW
to force the master into a wait state) if necessary due to internal high-priority tasks.
The slave/master interface can be used both for writing (e.g. sending commands) or reading (e.g. requesting
status). An additional GPIO pin on the SWA52 (Ex. GPIO24), can be used to notify the I2C master when a
pending message is ready to be sent.
The ATM210 slave interface responds to the 7-bit slave address 1000000 (0x40) as shown in picture below.
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JUN 10,2019