Specifications

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o Frame Relay
o Multiprotocol Label Switching (MPLS) Circuit Cross-connect
o Point-to-Point Protocol (PPP)
§ 4-MB parity-protected SSRAM memory
§ Hot insertion and removal
Supported PICs
An M160 chassis has eight FPC slots, each one supporting 12.8-Gbps full-
duplex throughput. Each slot can contain an FPC1, FPC2, or OC-192c/STM-
64 SONET/SDH PIC. The FPC1 and FPC2 can contain up to four PICs other
than the OC-192c/STM-64 SONET/SDH.
When you install an FPC with PICs into an operating router, the Routing
Engine downloads the FPC software, the FPC runs its diagnostics, and the
PICs on the FPC are enabled.
FPC ASICs
Each FPC contains two Packet Director ASICs and four I/O Manager ASICs.
The Packet Director ASICs balance and distribute packet loads across the
four I/O Manager ASICs per FPC. Since each Switching and Forwarding
Module (SFM) represents 40 Mpps of lookup and 40 Gbps of throughput,
and since the Packet Director ASICs balance traffic across the I/O Manager
ASICs before it is forwarded to the SFM, the result is aggregated forwarding
of 160 Mpps and aggregated throughput of over 160 Gbps.
The I/O Manager ASICs support wire-rate packet parsing, packet prioritizing,
and queuing. Each I/O Manager ASIC divides the packets, stores them in
shared memory, and re-assembles the packet for transmission.
The Distributed Buffer Manager ASICs on each M160 SFM manage this
memory. This single-stage buffering improves performance by requiring only
one write to and one read from shared memory. There are no extraneous
steps of copying packets from input buffers to output buffers as in other
architectures.
Class of Service
The FPCs support a rich CoS implementation featuring the following
mechanisms.
§ Four queues per physical interface
§ Classification based on the IP precedence value, the incoming logical or
physical interface, or the destination IP address
§ Weighted Round Robin queue servicing based on configurable weights
§ Random Early Detection congestion management
§ Configurable memory allocated to each queue
The FPCs support CoS queuing mechanisms for each PIC. You can
configure the amount of memory allocated on up to four priority queues with
per-port granularity. You can also configure the weights used in the
Weighted Round Robin algorithm that services the queues.
The FPCs queue outbound packets based on the IP precedence value, the
incoming logical or physical interface, or the destination IP address.
The FPCs also apply Random Early Detection on a per-queue basis in the
form of drop probability profiles. The probability that a packet will be dropped
is a function of the level of congestion in the queue. You can configure two
drop profiles for each queue: one for traffic that was received within a
bandwidth threshold agreement set with a customer and one for traffic that
was received out of profile. The FPC also supports per-queue rate shaping
on output.
For more information, refer to the following datasheet :
FPCs for the M160 Router
PIC
PIC
PIC
Physical
Interface
Card (PIC)
Buffer
Memory
I/O
Mgr
I/O
Mgr
I/O
Mgr
I/O
Mgr
PD
In
PD
Out
PIC
PIC
PIC
Physical
Interface
Card (PIC)
Buffer
Memory
I/O
Mgr
I/O
Mgr
I/O
Mgr
I/O
Mgr
PD
In
PD
Out
A logical View of the
M160 High-
bandwidth Flexible
PIC Concentrator
(FPC2)