Specifications

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packets, stores them in shared memory, and re-assembles the packet for
transmission.
The Distributed Buffer Manager ASICs on the control board manage this
memory. This single-stage buffering improves performance by requiring only
one write to and one read from shared memory. There are no extraneous
steps of copying packets from input buffers to output buffers as in other
architectures.
Class of Service
The FPCs support a rich CoS implementation featuring the following
mechanisms.
§ Four queues per physical interface
§ Classification based on the IP precedence value, the incoming logical or
physical interface, or the destination IP address
§ Weighted Round Robin queue servicing based on configurable weights
§ Random Early Detection congestion management
§ Configurable memory allocated to each queue
The FPCs support CoS queuing mechanisms for each PIC. You can
configure the amount of memory allocated on up to four priority queues with
per-port granularity. You can also configure the weights used in the
Weighted Round Robin algorithm that services the queues.
The FPCs queue outbound packets based on the IP precedence value, the
incoming logical or physical interface, or the destination IP address.
The FPCs also apply Random Early Detection on a per-queue basis in the
form of drop probability profiles. The probability that a packet will be dropped
is a function of the level of congestion in the queue. You can configure two
drop profiles for each queue: one for traffic that was received within a
bandwidth threshold agreement set with a customer and one for traffic that
was received out of profile. The FPC also supports per-queue rate shaping
on output.
For more information, refer to the following datasheet :
FPC for M20 and M40 Routers
2.10.8.2 FPCs for the M160 Router
Flexible PIC Concentrators (FPCs) on the M160™ Internet backbone router
house the Physical Interface Cards (PICs), delivering industry-leading
density and seamless integration into a wide rage of backbone
environments. These FPCs, known as FPC1 and FPC2, connect the PICs to
the rest of the router so that incoming packets are then forwarded across the
midplane to the appropriate destination port.
Features
§ High-density port concentration
§ 12.8-Gbps full-duplex aggregate throughput per FPC
§ Two Packet Director ASICs for dispersing and balancing packets across
the I/O Manager ASICs
§ Four I/O Manager ASICs for wire-rate parsing, prioritizing, and queuing
of packets
§ Each I/O Manager ASIC has 64-MB SDRAM, which is 256 MB of buffer
memory per FPC
§ ASIC-based framing and forwarding
§ Single-stage buffering system
§ Layer 2/Layer 3 Framing
§ Class of service (CoS) support
§ Encapsulations
o Cisco High-level Data Link Control (HDLC)
M160 High-
bandwidth Flexible
PIC Concentrator
(FPC2)
M160 Flexible PIC
Concentrator (FPC1)