Specifications
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T1/E1 to OC-48/STM-16. The Internet Processor also offers rich packet
filtering and sampling capabilities without sacrificing performance. The
Internet Processor II is housed on the Forwarding Engine Board (FEB) which
is serviceable from the rear of the chassis.
The FEB also houses the Memory Manager ASICs, which spray packets
across the shared memory, and the I/O Manager ASICs, which handle the L2
rewrite and the CoS queuing functionality. On the M160, M40, and M20, the
I/O Manager is located on the FPC, however M10/M5 has integrated FPC
functionality into the FEB.
The M10/M5 forwarding engine supports the same, hardware-based class-
of-service, packet filtering, and sampling feature set that is supported by the
M160, M40 and M20. These features include policing, classification, priority
queuing, Random Early Detection (RED) congestion control, inbound and
outbound packet filtering, and performance-based sampling.
2.9.2 Routing Engine
The M10/M5 RE is a compact-PCI-based subsystem that features a 333
MHz Pentium II processor with 256 or 768 MB DRAM stuffing options. The
routing engine is capable of supporting 100s of simultaneous BGP peers and
managing 1000s of virtual connections. The RE also provides three bootable
storage media, including a primary 80 MB non-rotating flash drive, a 6.4 GB
hard disk drive, and a removable 110 MB flash PC card. The fixed flash drive
acts as a primary boot device. The hard disk is a secondary boot device and
can be used for bulk storage. The PC card is also a secondary boot device
but is used primarily for image transfer. The RE is accessible through a
10/100 Ethernet management interface and console and auxiliary serial
ports, all of which are presented on the M10/M5 craft interface.
2.9.3 Interfaces
The M10/M5 supports hot insert and removal of ejector PICs. There is an
ejector handle on the faceplate of each PIC that ejects the PIC when pulled.
Both single-wide, and quad-wide PICs have their own ejection mechanism.
The hot swap implementation for the M10/M5 is very similar to that of the
M160. For removal, the user presses a PIC online/offline button on the
chassis prior to removal and the software will be able to detach the PIC
gracefully from the system. When a PIC is inserted into the system, the
user must press the PIC online button for at least 3 seconds to allow the
software to recognize the PIC and initiate bringing the PIC online. The
software will not automatically bring PICs online when running. The button
must be pressed. The only time that PICs are automatically brought online is
when they are already inserted in the chassis when the PFE is booted. Every
time a PIC is brought online or offline, there is a PFE logical reset.
There is no FPC as a FRU on M10 or M5. Instead, FPC functionality is
included in the FEB. M10/M5 PICs are NOT supported by M20/M40 and
there are no plans for such support in the future. Similarly, current M20/M40
PICs are not supported by the M10/M5.
All PIC variants available for M20/M40 are available for the M10/M5.
Additionally, each future PIC will have two variants: one for M10/M5 and one