Specifications

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be to redirect the packet to a particular interface (future functionality). After the
lookup is performed, packet filters can be configured and applied to particular
outgoing interfaces to support the filtering of traffic destined for particular next
hops. Counters can be configured to track the number of matches for each filter.
The ability to configure various combinations of these building blocks, combined
with ASIC-based performance, makes the Internet Processor II a powerful and
flexible tool for a number of applications.
Additional Architectural Enhancements
In addition to the enhanced building block functionality, the Internet Processor II
architecture brings other feature enhancements.
§ Statistical Sampling. The Internet Processor II architecture supports
statistically valid sampling whereby the user configures the percentage of
traffic to be sampled. Additionally, a firewall filter can be applied to influence
which packets are candidates for sampling (ie sample all HTTP traffic
destined for interface X)
§ Per-packet Load Balancing without Packet Reordering. With the Internet
Processor II, load-sharing is deterministic, based on a hash calculated over
each packet (eg source-destination prefix information). The hash will have
the same result for all the traffic within a TCP flow so the traffic within a flow
will all go through the same link, avoiding the possibility of reordering.
Internet Processor II Performance
Aside from its flexibility, the most compelling feature of the Internet Processor II
ASIC is its performance. The Internet Processor II key differentiator is its ability to
support value-added services, such as filtering, without sacrificing performance.
With no filters configured, the Internet Processor II runs at rates in excess of 40
million pps. The performance impact of applying filters will depend on the size
and complexity of the filter but for practical purposes, performance impact will be
minimal for most filters. Performance is maintained because of the Internet
Processor II ASIC-based design, as well as the fact that once configured, filtering
programs are compiled and optimized by the RE before sending them to the
Internet Processor II. Additionally, the PFE pooled resource design of the M20
and M40 platforms and the inherent over-sized design of the Internet Processor II
with respect to interfaces, combine to ensure additional performance head-room
even with value-added features turned on.
Conclusion
The Internet Processor II provides fundamentally breakthrough technology that
will allow customers to deploy a new class of performance-based features. It will
also enable many applications that were previously infeasible due to performance
constraints. Additionally, the Internet Processor II’ s functionality is so flexible, it is
likely that customers will find new ways of using it that will drive future application
development.
Because the Internet Processor II functionality is so rich, related features will be
introduced over the course of several releases. JUNOS 4.0 supports filtering,
sampling, and load balancing without packet reordering. Additional functionality
will be deployed in future releases.