Specifications

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2.5 M20, M40 and M160 Internal Architecture
2.5.1 Internal Architecture of the M20 and M40
The M20 and M40 architecture consists of a Routing Engine (RE), a Packet-
Forwarding Engine (PFE), and various I/O cards called PIC (Physical Interface
Cards) which are inserted on master interface modules called FPC (Flexible PIC
Concentrators) . The RE maintains the routing table and routing code, including
SNMP functionality. The PFE is dedicated solely to the forwarding of packets in
the fastest way possible. This separation ensures that high levels of route
instability do not impact the performance of the PFE and likewise, extremely high
volumes of traffic do not impact the ability of the RE to maintain peer relationships
and calculate routing tables.
Distributed
Buffer
Manager
ASIC
Distributed
Buffer
Manager
ASIC
Internet
Processor II
ASIC
Shared Memory
PIC
I/O
card
I/O
Manager
ASIC
PIC
I/O
card
I/O
Manager
ASIC
Packet
Forwarding
Engine
Flexible PIC
Concentrator
Packet IN Packet OUT
Forwarding
Table
Routing
Table
Forwarding
Table
Routing
Engine
A key distinction of the M40 PFE (Packet Forwarding Engine) is a set of Juniper
Networks-developed custom application-specific integrated circuits (ASICs) that
deliver a comprehensive hardware-based system for route lookups, buffer
management, switching, and encapsulation/decapsulation functions. To ensure a
non-blocking forwarding path, all channels between the ASICs are oversized,
dedicated paths.
The heart of the M40 PFE is the Internet Processor ASIC. The Internet
Processor supports a lookup rate of over 40 million packets per second (for a
routing table with 80,000 entries and more) to deliver true wire-speed forwarding
performance. With over one million gates, the Internet Processor is the largest
and fastest route lookup ASIC ever implemented on a router platform and
deployed in the Internet.
The Distributed Buffer Manager ASIC coordinates the M40 router's shared
memory system. The advantages of a shared-memory system include reduced
complexity, elimination of head-of-line blocking typically associated with multi-
stage buffering systems, multicast forwarding, and efficient use of memory
bandwidth.
The I/O Manager ASIC supports wire-rate packet parsing, packet prioritizing, and
queuing disciplines. On SONET/SDH, ATM, and Gigabit Ethernet PICs,
customized ASICs perform the framing functions.
Thus to summarize, there are :
§ 1 Internet Processor ASIC,
§ 2 Distributed Buffer Manager ASICs
§ 1 I/O Manager ASIC per FPC
§ 1 Media specific ASIC (Sonet/ATM/Gigabit Ethernet) per PIC.