M-xxx SERIES PRODUCT DESCRIPTION October 26th, 2000
Sommaire 1. INTRODUCTION................................................................................................................................................................ 5 1.1 JUNIPER NETWORKS : TECHNOLOGY OVERVIEW................................................................................................5 1.1.1 Challenge: Reliability with Rapid Growth ................................................................................................5 1.1.
2.10.1 2.10.2 2.10.3 2.10.4 2.10.5 2.10.6 2.10.7 2.10.8 2.10.9 2.10.10 2.10.11 2.10.12 2.10.13 2.10.14 2.10.15 2.10.16 2.10.17 2.10.18 2.10.19 2.10.20 3. M20 Specifications........................................................................................................................................59 M40 Specifications........................................................................................................................................61 M160 Specifications........................
.1.5 4.1.6 4.1.7 Software Errors............................................................................................................................................120 Hardware Errors...........................................................................................................................................121 Network Level Reliability...........................................................................................................................122 4.
1. INTRODUCTION 1.1 1.1.1 Juniper Networks : Technology Overview Challenge: Reliability with Rapid Growth Internet backbone networks are constantly under pressure to scale rapidly in order to accommodate customer demands for faster response times and greater reliability. At the same time, routing and packet forwarding technologies have lagged Internet growth. This lag has increased the operational challenge of maintaining stability in the face of rapid network growth.
infrastructures. It is purpose built for large backbone cores, with features enabled for future migration to the backbone edge. The M160 router offers aggregate route lookup rates in excess of 160 Mpps for wire-rate forwarding performance and an aggregate throughput exceeding 160 Gbps. It is the first router to offer a truly concatenated OC-192c/STM-64 PIC with throughput of 10-Gbps full duplex and market-leading port density with up to 32 OC48c/STM-16 PICs per chassis or 64 per rack.
1.2 JUNOS Internet Software: Traffic Engineering and Control Protocols and software tools, which are used to control and direct network traffic, are critical to an Internet backbone routing solution. In fact, software control is made more important by the fact that the size and complexity of backbone networks are increasing at a time when service providers are looking to differentiate themselves through value-added service offerings.
1.3 § Distinguish between temporary traffic bursts that can be accommodated by the network and excessive offered load likely to swamp network resources. § Work cooperatively with traffic sources to avoid TCP slow start oscillation that can create periodic waves of network congestion. § Provide fair bandwidth reduction to reduce traffic sources in proportion to the bandwidth being utilized.
Potential applications within an IP Service Provider Network for the M-xxx are explained below. 1.4.1 Backbone Routing Juniper proposes using the M-xxx Internet backbone routers for interconnecting the different sites in an IP Service Provider Network. The advantage of using a high-speed backbone router for this purpose is that you can use either E3/DS3 interfaces, ATM interfaces, which scale up to OC12 speeds today or Packet over SONET (POS) interfaces, which scale up to OC48.
1.6 Juniper Networks Internet Backbone Routers Advantages Features Benefits Architecture Highly Integrated ASIC forwarding § § § § § § Routing and forwarding performance cleanly separated § Routing fluctuations and network instability do not impede packet Fully sized and designed to perform lookups at a rate of 160 Mpps. Scales well with large, complex forwarding tables. Full utilization of expensive circuits. Packet size does not affect forwarding performance. Rock solid system stability.
Features Benefits Performance -based IP Services Performance-based packet filtering of inbound and outbound traffic based on any combination of matches § Source IP address § Destination IP address § DiffServ byte § IP protocol § IP fragmentation offset and control fields (Offset, MF, DF) § Source transport port § Destination transport port § TCP control bits (SYN, ACK, FIN) You can configure one input filter and one output filter for each logical interface.
2. THE JUNIPER NETWORKS INTERNET BACKBONE ROUTER PLATFORMS 2.1 The M20, M40 and M160 Internet Core Backbone Routers The Juniper Networks’ M20T M , M40T M and M160T M Internet Core Backbone Routers are designed to provide wire-speed forwarding rates across multiple optical interfaces for all packet sizes. The M20 and M40 are intended to fill multiple roles in large enterprises, ISP and carrier super-POPs, playing the role of high speed access, aggregation, cross-connect, and core backbone device.
General Description The M160 represents the next generation platform for Juniper Networks. Building on the M40 product the M160 provides: § High Density OC-48c interfaces (up to 32 ports per system) § OC-192c interfaces to provide a higher interface speed and to provide high speed optical connections to WDMs (available Q2 2000) § The ability to build a system with no single point of failure. § Enhance installation and servicability.
2.2 The M20 Hardware System The M20 Internet Backbone Router provides high-speed interfaces for large networks and network applications, such as those supported by Internet backbone service providers. Application-specific integrated circuits (ASICs), a definitive part of the router design, enable the router to achieve data forwarding rates that match current fiber-optic capacity.
§ Cooling system —The cooling subsys tems have redundant components, which are controlled by the SSB. If a fan fails, the remaining fans provide sufficient cooling for the unit indefinitely. Chassis The router chassis is a rigid sheet metal structure that houses all the other router hardware components. The chassis is 14 in. (36 cm) high, 19 in. (48 cm) wide, and 21 in. (54 cm) deep. The chassis has a mounting system that installs into standard 19-in.
§ PICs—One to four PICs can be attached to each FPC. PICs provide support for various network media, including OC-12 ATM, OC-48 SONET, Gigabit Ethernet, and DS3. Midplane The router midplane forms the back of the card cage. The FPCs, SSB, and craft interface install into the midplane from the front of the chassis. Fan trays plug into the midplane from both the front and rear of the chassis. Power supplies and the Routing Engine plug into the midplane from the back of the chassis.
§ § o 33-MHz PCI bus—Connects system ASICs Storage components o Four slots of 1-MB RAM for forwarding tables associated with ASICs o 64-MB DRAM for the microkernel o EEPROM containing the SSB’s serial number and board release version o 512-KB boot flash EPROM (programmable on the board) System interfaces o Three LEDs o 100-Mbps Fast Ethernet link for internal interface to the Routing Engine and FPC boards o RS-232 debugging port (DB-25 connector) o 19.
type. Before transmitting outgoing data packets, the PICs encapsulate the packets received from the FPCs. Each PIC is equipped with a media-specific ASIC that performs control functions tailored to the PIC’s media type. PICs are field-replaceable. To remove a PIC, you first remove its host FPC, which is hot-removable and hot-insertable. PIC LEDs Each port on each PIC has one LED, located on the PIC faceplate above the transceiver. Each LED has four different states.
The Routing Engine LEDs on the craft interface report the status of the Routing Engine. They are located above and below the Juniper Networks logo near the middle of the craft interface. Routing Engine Offline Buttons Routing Engine offline buttons are used to take the Routing Engine offline in case the Routing Engine needs to be replaced. The offline buttons are located to the right of the Routing Engine.
2.3 The M40 Hardware System The M40 Internet Backbone Router provides high-speed interfaces for large networks and network applications, such as those supported by Internet backbone service providers. Application-specific integrated circuits (ASICs), a definitive part of the router design, enable the router to achieve data forwarding rates that match current fiber-optic capacity.
Component Redundancy The router is designed so that no single point of failure can cause the entire system to fail. The following major hardware modules are redundant: § § § Host module—Comprises a Routing Engine and SCB functioning together. The router can have one or two host modules. Power supplies —The router has two power supplies, which share the load evenly. If one of the power supplies fails, the second power supply can supply full power to the router’s components.
o o o o Two asynchronous serial ports on the craft interface—Connect a console, laptop, or modem for direct or local area network management access to the M40 router. Ethernet port (10 or 100 Mbps, with an autosensing RJ-45 connector) on the craft interface—Connects the Routing Engine to a terminal server or an SNMP management station for outof-band management of the M40 router. System LEDs on the craft interface—Green LEDs indicate OK status and red LEDs indicate Fail status.
§ § a “high temp” alarm. If the sensor exceeds the second threshold, the Routing Engine initiates a system shutdown. Transfer of exception and control packets—The Internet Processor ASIC on the SCB passes exception packets to a microprocessor on the SCB, which processes almost all of them. The remainder are sent to the Routing Engine for further processing. Any errors originating in the Packet Forwarding Engine and detected by the SCB are sent to the Routing Engine using SYSLOG messages.
Routing Engine downloads the FPC software, the FPC runs its diagnostics, and the PICs on the FPC slot are enabled. Routing functions continue uninterrupted.
§ Alarm mode—Displays alarm conditions whenever the red or yellow alarm LED is lit. Alarm Relay Contacts The craft interface contains two sets of relay contacts for alarms. You can cable the alarm relay contacts to an external alarm device. Whenever a system condition triggers either the red or yellow alarm on the craft interface, the alarm relay contacts also are activated. Routing Engine Ports The Routing Engine has three ports for connecting external management devices.
through vents located in the upper impeller tray. The air is channelled past the Packet Forwarding Engine components, keeping them cool. During normal operation, both pairs of impellers function at less than full capacity. A temperature sensor on the backplane controls the speed of the impellers. If you remove one impeller tray, the temperature of the backplane increases and the speed of the remaining pair of impellers adjusts automatically to keep the temperature within the acceptable range.
2.4 The M160 Hardware System The M160 Internet Backbone Router is a complete routing system that provides SDH/SONET, ATM, Gigabit Ethernet, and other high-speed interfaces for large networks and network applications, such as those supported by Internet service providers (ISPs). Application-specific integrated circuits (ASICs), a definitive part of the router system design, enable the router to achieve data forwarding rates that match current fiber-optic capacity.
§ § Hot-insertable and hot-removable—You can remove and replace these components without powering down the router or disrupting the routing functions. The power supplies, SFMs, PICs and FPCs are hot-insertable and hot-removable. Hot-pluggable—You can remove and replace these components without powering down the router, but the routing functions of the system are interrupted when the component is removed. The PCGs, the MCS, and the Routing Engine are hot-pluggable.
§ § § § the chassis, and the SFMs, Routing Engine, MCS, and PCGs install horizontally from the rear of the chassis. Switching and Forwarding Modules (SFMs)—From one to four SFMs can be installed into the rear of the chassis. Flexible PIC Concentrators (FPCs)—From one to eight FPCs can be installed into the front of the chassis. Each FPC has a set of connectors for attaching one or more PICs.
§ § § § § § § Two Distributed Buffer Manager ASICs—One sends packets to the output buffer and oneforwards notification to the I/O Manager ASICs on the FPCs. Internet Processor II ASIC—Performs route lookups. 8-MB of parity-protected SSRAM. Processor subsystem —Comprises one PowerPC603e processor, 256KB of parity-protected Level 2 cache, and 64-MB of parity-protected DRAM. This subsystem handles exception packets and management of the SFM. EEPROM—Stores the serial number and revision level.
FPC1 and FPC2 The router supports two types of FPC: § § FPC1—Supports single-port OC-12 and Gigabit Ethernet PICs. FPC2—Supports higher-speed OC-48 and Tunnel PICs. The router can operate with any combination of FPC1s and FPC2s installed. The installation and removal of the two FPC types is identical. PICs that can be inserted on an FPC2 are distinguished by having an offline button on their faceplate. The FPC1 has built-in offline buttons for the PICs it holds.
Each PCG contains the following components: § § § § 125-MHz system clock generator EEPROM—Stores the serial number and revision level of the PCG Three LEDs—one blue MASTER, one green OK and one amber FAI L Offline button for module removal PCG LEDs Three LEDs are located on the faceplate of the PCG. Table 6 describes the functions of these LEDs. Host Module The host module provides the routing and system management functions of the router.
The MCS works with the Routing Engine to provide control and monitoring functions for router components and to provide SONET clocking for the router. The MCS installs into the midplane from the rear of the chassis. The router can be equipped with up to two MCSs for redundancy. If two MCSs are installed, one acts as the master MCS and the other acts as backup. If the master MCS fails or is removed, the backup restarts and becomes the master MCS.
The Connector Interface Panel (CIP) is located at the left side of the FPC card cage. The CIP consists of connectors for the Routing Engines, Building Integrated Timing Source (BITS) interfaces for the MCS, and alarm relay contacts. Routing Engine Ports The CIP has two sets of ports for connecting the Routing Engines to external management devices. You can use the command-line interface on these management devices to configure the router.
§ § Front Cooling Subsystem—An upper impeller and a lower fan tray cool the FPCs, the PICs and the midplane. Rear Cooling Subsystem —A pair of impellers cools the SFMs, the host module, the PCGs, and the power supplies. The MCS monitors the temperature of the router’s components. When the router is operating normally, the impellers and fans function at lower than full speed.
2.5 2.5.1 M20, M40 and M160 Internal Architecture Internal Architecture of the M20 and M40 The M20 and M40 architecture consists of a Routing Engine (RE), a PacketForwarding Engine (PFE), and various I/O cards called PIC (Physical Interface Cards) which are inserted on master interface modules called FPC (Flexible PIC Concentrators) . The RE maintains the routing table and routing code, including SNMP functionality. The PFE is dedicated solely to the forwarding of packets in the fastest way possible.
In addition to ASICs, there is a 200 MHz PowerPC 603e processor that manages the link between the RE and PFE, manages forwarding table updates, manages ASICs and environmental systems and controls craft interface. The RE which is an Intel-based Compact PCI platform has a 233 Mhz Pentium processor. Note that this is used only for routing functions only and not for packet forwarding. 2.5.
The Routing Engine maintains the routing tables and controls the routing protocols. It consists of an Intel-based PCI platform running JUNOS software. Another key architectural component is the Miscellaneous Control Subsystem (MCS), which provides SONET/SDH clocking and works with the Routing Engine to provide control and monitoring functions. The architecture ensures industry-leading service delivery by cleanly separating the forwarding performance from the routing performance.
Media-specific ASICs The media-specific ASICs perform physical layer functions, such as framing. Each PIC is equipped with an ASIC or FPGA that performs control functions tailored to the PIC's media type. SDH/SONET Manager ASIC § § § ATM Manager ASIC DS-3 Manager FPGA Gigabit Ethernet Manager ASIC Packet Forwarding Engine The PFE provides Layer 2 and Layer 3 packet switching, route lookups, and packet forwarding.
notification of outgoing packets. There are four SFMs, thus ensuring automatic failover to a redundant SFM in case of failure. Routing Engine The Routing Engine maintains the routing tables and controls the routing protocols, as well as the JUNOS software processes that control the router’s interfaces, the chassis components, system management, and user access to the router. These routing and software processes run on top of a kernel that interacts with the PFE.
PD Out Buffer Memory The cells are then reassembled in the I/O Manager ASIC on the outgoing FPC and passed to the chip on the PIC for encapsulation and transmission. PIC The pooled memory source is deliberately oversized, and is comprised of memory provided by all available FPCs. The size of the memory pool ensures that each cell is never held up waiting for available buffer memory, and therefore the forwarding process is never unduly interrupted or delayed.
Forwarding tables exist in the RE and in the PFE. In the RE, forwarding tables are present at both the routing software and operating system levels. The routing software must be aware of the forwarding table because the routing software is the element of the system that chooses which routes are selected for use. The routing software tells the operating system what its forwarding table should be. Finally, the PFE’s forwarding table is created by flushing the operating system’s forwarding table into the PFE.
The M20/M40/M160 has a wire rate performance for all packet sizes (40 to 9192 bytes) for all types of interface cards. The delay of the packet within the system is ~ 7 microseconds as measured from the last bit in to first bit out. 2.5.8 The Internet Processor II ASIC The Internet Processor II is the second generation, enhanced version of the Internet Processor ASIC that forms the core of the M40 and M20 Packet Forwarding Engines (PFEs).
be to redirect the packet to a particular interface (future functionality). After the lookup is performed, packet filters can be configured and applied to particular outgoing interfaces to support the filtering of traffic destined for particular next hops. Counters can be configured to track the number of matches for each filter.
2.6 Congestion Control Traffic Rate Policing Traffic Classification Priority Queuing Congestion Avoidance W R R RED 100% Stream • IP Precedence bits • MPLS CoS bits • Incoming Physical Interface 100% 100% PLP=1 PLP=0 • Incoming Logical Interface • Source or Destination IP address 2.6.
percent full, a non-PLP packet is never dropped (it matches the stream profile, but not the non-PLP profile), and a PLP packet is always dropped (it matches both the stream and PLP set profiles and in the PLP profile has a 100-percent drop probability). Figure: RED Drop Profiles To randomize the drop event, RED generates a random number for the packet in the queue and plots this number to the Y axis of the drop profile graphs shown in the figure above.
In the threshold option, specify the bucket threshold, which controls the burstiness of the leaky bucket mechanism. The larger the value, the more bursty the traffic, which means that over a very short amount of time, the interface can receive or transmit close to line rate, but the average over a longer time is at the configured bucket rate. The threshold can be a value from 0 through 65535.
from subscribers that were received at rates that exceed an agreed upon threshold limit and packets that are within the threshold limit. Above-threshold packets can be dropped more aggressively. A packet is dropped only if both the queue profile and the port profile indicate to drop the packet. A port profile is used to ensure that packets are not dropped when other queues are underutilized. Each outgoing PIC interface--either logical (I.e.
After the route lookup, packet notifications are sent to the outgoing FPC for transmission. The I/O manager on the outgoing FPC houses the COS queues for all of the interfaces on the FPC. The packet notifications are queued based on IP Precedence Bit information, incoming physical or logical port, destination IP address, or application type (e.g. VoIP, telnet, http). The classification based on application type will be available in a future release of JUNOS.
§ § § § Policing on a per-class basis within a logical interface (e.g., on a DS-3 allow 2 Mbps of traffic marked with the "gold" DiffServ Code Point value, 5 Mbps of traffic marked with the "silver" DiffServ Code Point value and an unlimited amount of traffic marked with the "bronze" DiffServ Code Point value). Policing on a "layer 4" profile. For example, allow an unlimited amount of SMTP traffic and mark it as low priority but police interactive HTTP traffic to some bandwidth threshold.
2.7.4 ATM Traffic Shaping The Mxxx ATM interfaces have their own support for traffic shaping on a per virtual circuit (VC) basis. Specifically, in Variable Bit Rate (VBR) mode, the ATM PICs support per VC configuration of the peak cell rate, sustained cell rate, burst size, and queue length. Typically, the Mxxx will transmit at the sustained cell rate.
To define limits to bandwidth utilization on a point-to-point interface or to limit buffer use, you need to include the shaping statement. For point-to-point interfaces, include the shaping statement at the [edit n i terfaces interface-name unit logical-unit-number] hierarchy level: [edit interfaces interface-name] user@host# show unit logical-unit-number { vci vpi-identifier.
2.8 Clock Source When configuring the Juniper Mxxx routers, you can configure the transmit clock on each interface and you also can configure the system clock reference clock source. For both router and interfaces, the clock source can be either the routers internal stratum 3 clock, which resides on the System Control Board (SCB), or an external clock that is received from on of the routers interfaces.
2.9 The M5 and M10 Internet Routers The M5 router The M10 router The M10/M5 is a compact, high-performance routing platform based on the ASIC-based M160/M40/M20 forwarding architecture (including the Internet Processor II) and JUNOS Internet software. As an extension of the M160/M40/M20 product line, the M10/M5 is targeted at a variety of Internet applications, including high-speed access, public and private peering, content sites, and backbone core networks. Only 5.
T1/E1 to OC-48/STM-16. The Internet Processor also offers rich packet filtering and sampling capabilities without sacrificing performance. The Internet Processor II is housed on the Forwarding Engine Board (FEB) which is serviceable from the rear of the chassis. The FEB also houses the Memory Manager ASICs, which spray packets across the shared memory, and the I/O Manager ASICs, which handle the L2 rewrite and the CoS queuing functionality.
for M20/M40 (and, in most cases, a third variant for M160). The table below lists the interfaces available for M10/M5, along with supported port densities.
2.9.6 Cooling System The M10/M5 cooling system circulates air side-to-side, using a single, removable fan tray. In addition, the M10/M5 power supplies have their own internal fans. The fan tray can be inserted or removed while the M10/M5 is powered up, without adversely affecting the system. If a fan should fail, a fan tray alarm will sound, indicating a need for service. The fan tray is a FRU and should be replaced as soon as possible following a fan failure. 2.9.
2.9.9.2 Public and Private Peering The M10/M5 is also an ideal solution for peering, both public and private. Peering links tend have higher utilization than subscriber access links of comparable speed. Thus, for peering, performance really matters. The Internet Processor II's 40 Mpps lookup performance enables providers to concentrate multiple peering links at up to gigabit speeds on a single chassis.
2.10 Products Specifications 2.10.
AC • AC input voltage: 90-264 VAC operating range Thermal Output • 5676 BTU/hour Environment • • • Temperature range: 0 to 40 degrees C Maximum altitude: 10,000 feet Relative humidity: 5% to 90% noncondensing Agency Approvals Safety • UL 1950 • CSA 22.2-No.
2.10.
• Agency Approvals Relative humidity: 5% to 90% noncondensing Safety • UL 1950 • CSA 22.2-No.
2.10.
• • Weight 370.5 lb / 168.
2.10.4 Summary of Power Supply Specifications Power Supply Specifications AC – Input Voltage Range M20 90-264 VAC M40 80-260 VAC AC – Maximum Input Current 13A at 90 VAC 8A at 208 VAC AC – Maximum Power Consumption DC - Input Voltage Range 1200 W 1680 W -140.5 to –72 VDC -38 to –75 VDC M160 -48 to –60 VDC DC – Output Voltage DC – Maximum Input Current DC – Maximum Power Consumption +48 V at 8 A, +8 V at 6 A, –48 at 60 A 24A at –48 VDC 35A at –48 VDC 65A at –48 VDC 1200 W 1664 W 2600 W 2.
2.10.
2.10.
2.10.8 Flexible PIC Concentrator Cards for Juniper Networks Routers Flexible PIC Concentrators (FPCs) house the Physical Interface Cards (PICs) and are installed in slots in the M20™, M40™, and M160™ Internet backbone routers. These intelligent, high-performance interface concentrators offer unparalleled interface density and flexibility.
packets, stores them in shared memory, and re-assembles the packet for transmission. The Distributed Buffer Manager ASICs on the control board manage this memory. This single-stage buffering improves performance by requiring only one write to and one read from shared memory. There are no extraneous steps of copying packets from input buffers to output buffers as in other architectures. Class of Service The FPCs support a rich CoS implementation featuring the following mechanisms.
§ § o Frame Relay o Multiprotocol Label Switching (MPLS) Circuit Cross-connect o Point-to-Point Protocol (PPP) 4-MB parity-protected SSRAM memory Hot insertion and removal Supported PICs An M160 chassis has eight FPC slots, each one supporting 12.8 -Gbps fullduplex throughput. Each slot can contain an FPC1, FPC2, or OC-192c/STM64 SONET/SDH PIC. The FPC1 and FPC2 can contain up to four PICs other than the OC-192c/STM-64 SONET/SDH.
2.10.9 POS Interfaces Specifications As demand for more bandwidth increases, service providers need to build out new, state-of-the-art, optical infrastructures to achieve greater backbone throughput and faster network response times. Juniper Networks, Inc. is at the forefront of routing infrastructure build-out, offering a complete range of SONET/SDH Physical Interface Cards (PICs) and supporting speeds from OC-3c/STM-1 through OC-192c/STM-64.
Descriptions § OC-3c/STM-1 The four-port OC-3c/STM-1 PIC provides an ideal solution for building backbones using high-speed OC-3c/STM-1 access circuits. This PIC delivers per-port 155-Gbps throughput at wire rate for an aggregate PIC throughput of 622 Mbps. It operates in concatenated mode. 4-port OC3/STM-1 POS PIC § OC-12c/STM-4 The one-port OC-12c/STM-4 PIC is ideal for migrating backbones to higher speeds while preserving the option for redundant circuits.
2.10.9.1 SONET/SDH PICs for M20 and M40 Routers Available Interfaces § OC-3c/STM-1 (concatenated mode) § OC-12c/STM-4 (concatenated and nonconcatenated modes) § OC-48c/STM-16 (concatenated and nonconcatenated modes) For more information, refer to the following datasheet : SONET SDH PICs for M20 and M40 Routers 2.10.9.
2.10.10 ATM Interfaces Specifications The ATM OC-3/STM-1 and ATM OC-12/STM-4 Physical Interface Cards (PICs) f o r M-series Internet backbone routers provide both the performance and the density to scale ATM-based backbones. They are useful for terminating ATM access circuits and for terminating ATM virtual circuits extending across a network backbone. ATM PICs are useful for terminating ATM access circuits and for terminating ATM virtual circuits extending across a network backbone.
OC-3/STM-1 The two-port OC-3/STM-1 PIC provides an ideal solution for building backbones or access networks using high-speed OC-3/STM-1 circuits. This PIC delivers perport 155-Mbps throughput at wire rate. Two-port OC3/STM-1 ATM PIC OC-12/STM-4 The one-port OC-12/STM-4 PIC is ideal for migrating backbones and access networks to higher speeds. The PIC delivers 622-Mbps throughput at wire rate.
Specifications The Juniper M-xxx Routers support the robust routing of IP datagrams over ATM OC-3/STM1 and ATM OC-12/STM4 interfaces. Point-to-multipoint support is available. RFC 1483 is supported. Routing mode is supported, bridging mode is currently not supported.
ATM OC-12/STM-4 PIC (Single-Mode & Multi-Mode) Parameter Max. Min. Spec. Aggregate Throughput (cells/second) 1,412,736 per int.
2.10.11 DS-3 Physical Interface Cards for M-xxx Routers The four-port DS-3 Physical Interface Card (PIC) for M-series Internet backbone routers provides high levels of DS-3 density, conserving valuable POP rack space. M-series DS-3 connections are increasingly used for connecting corporations and other high-bandwidth subscribers to Internet backbones for greater throughput and faster response times. 4-port DS-3 PIC for M20 and M40 routers Features § Wire-rate throughput on all ports at speeds up to 44.
2.10.13 Channelized OC-12 to DS-3 Physical Interface Card The rapid growth of the Internet and Internet-related applications are driving demand for a scalable high-speed access infrastructure. As the number of subscribers outgrow N x DS-0 and DS-1 access circuits, h t ere is an increasing need to deliver a rich set of services over faster interfaces and to ease provisioning of higher densities of high-speed circuits.
2.10.15 T1 Physical Interface Card for M-series Routers The four-port T1 Physical Interface Card (PIC) for the M-series Internet backbone routers offers high-density, clear-channel and fractional-T1 (1.544 Mbps) connectivity. The T1 PIC leverages the raw wire-rate performance and rich packet processing capabilities of the M-series platforms, enabling you to support a wide range of services, such as packet filtering, class of service, rate limiting, and sampling. Features § Supports speeds up to 1.
2.10.17 Fast Ethernet Physical Interface Card for M-series Routers The four-port Fast Ethernet Physical Interface Card (PIC) fo r M-series Internet backbone routers provides economic 100-Mbps performance with high reliability and low maintenance costs. The Fast Ethernet PIC is an attractive interface for a variety of applications, including intra-POP switching, content Web hosting, and both public and private peering.
§ § One tri-color LED on the PIC faceplate that indicates overall status of the PIC Per-port pair of LEDs indicating Link OK and Receive Activity Additionally, the Gigabit Ethernet PIC works with the Internet Processor II™ ASIC to support filtering, sampling, load balancing, class of service, and rate limiting. 802.1Q VLAN Support The Gigabit Ethernet PIC supports 802.1Q VLANs.
2.10.19 Tunnel Services Physical Interface Card The Tunnel Services Physical Interface Card (PIC) for M-series Internet backbone routers enables you to leverage your existing IP infrastructure to carry multiple traffic types. With the Tunnel Services PIC, the routers can function as the ingress or egress point of an IP-IP unicast tunnel, and generic routing encapsulation (GRE) tunnel, or a Protocol Independent MulticastSparse Mode (PIM-SM) tunnel.
2.10.20 Frame Relay Specifications Frame Relay is supported on all serial and POS interfaces as per RFC 1490. You can configure Frame Relay for the following types of connections: § Point-to-Point Connection § Point-to-Multipoint Connection § Multicast-Capable Frame Relay Connection The M-xxx Routers will typically serve as a Frame Relay edge device. You may also use Circuit Cross Connect (CCC) in which case the M-xxx behaves as a Layer-2 switch.
3. JUNOS SOFTWARE SPECIFICATIONS 3.1 JUNOS Software Architecture All JUNOS routing protocols were developed in-house. JUNOS has been running production traffic in the largest ISP networks in the Internet since the first half of 1998. JUNOS implements “bug-for-bug” compatibility modes ensuring correct operation with leading vendor’s routers. Juniper’s software team has extensive experience implementing most widely used routing software in the Internet.
JUNOS Software Routing Engine Command-line Interface System Management Processes Routing Protocols Control Functions Kernel Intel-based PIC platform Routing Engine and JUNOS Software Architecture The Routing Engine connects directly to the Packet Forwarding Engine. This separation of routing and forwarding performance ensures that the Routing Engine never processes transit packets.
Routing Kernel Process The Routing Engine kernel provides the underlying infrastructure for all the JUNOS software processes. In addition, it provides the link between the routing tables and the Routing Engine's forwarding table. It is also responsible for all communication with the Packet Forwarding Engine, which includes keeping the Packet Forwarding Engine's copy of the forwarding table synchronized with the master copy in the Routing Engine. 3.1.
How the Routing and Forwarding Tables Are Synchronized Routing Engine Routing Table Forwarding Table Packet Forwarding Engine Internet Processor ASIC Forwarding Table The JUNOS routing protocol process is responsible for synchronizing the routing information between the routing and forwarding tables. To do this, the routing protocol process calculates the active routes from all the routes in the routing table and installs them into the forwarding table.
If nondeterministic routing table path selection behavior is not configured (that is, if the path-selection cisco-nondeterministic statement is not included in the BGP configuration), for paths with the same neighboring AS numbers at the front of the AS path, prefer the path with the lowest multiple exit discriminator (MED) metric. Confederation AS numbers are not considered when deciding what the neighbor AS number is.
Default Route Preference Values : 3.1.
§ § § § § 3.1.3.3 Traffic engineering protocols § § § § 3.2 PIM sparse mode and dense mode—Protocol-Independent Multicast is a multicast routing protocol. PIM sparse mode routes to multicast groups that might span wide-area and interdomain internets. PIM dense mode is a flood-and-prune protocol. MSDP—Multicast Source Discovery Protocol allows multiple PIM sparse mode domains to be joined.
3.2.1 Static Routing JUNOS allows routes to be created statically through configuration that point either to real interfaces and therefore result in traffic being forwarded, or that can point to null interfaces such that the packets are dropped. The blackhole routes can take one of two forms: ones where ICMP Destination Unreachable messages are sent or ones where the packets are silently discarded 3.2.
3.2.4 § block LSP flooding on a per-interface basis (implementation of group feature) § multiple adjacencies to the same Intermediate System, and path selection based on the metrics corresponding to those adjacencies § intelligent routing between level 1 and level 2 to achieve IGP global routing optimization - The Open Shortest Path First (OSPF) Internal Gateway Protocol (IGP) includes support for a backbone area and many stub areas.
§ route flap dampening - The Juniper BGP4 implementation contains the route dampening feature and its configuration includes the ability to enable and disable it as well as to configure the various penalties, half-lives and suppression thresholds. Disabling the default route flap damping behavior can be based on policy, on a per prefix and/or per peer basis, as per the example below : [edit policy-options] damping dont-damp { disable; } policy-statement test { from { route-filter 198.41.0.
conveniently strip all communities that start with specific Autonomous System Numbers. § route filtering based on prefix and ASN - The policy engine can be used to apply lists of prefixes and/or ASNs against a particular BGP peer for filtering inbound announcements and similar filters can be applied to outbound announcements towards a peer.
in the routing table. Additional CLI commands allow the user to display prefixes which share some set of community attributes. Finally, the CLI allows the user to display the prefixes being suppressed because of route flap as well as the accumulated dampening state on a per-prefix basis.
and origin. For match conditions, you also can specify lists of routes, which are grouped so that a common action can be applied to them.
Other features supported by the JUNOS routing policy server are : § Policy Arithmetic Provides the ability to do arithmetic in policy. For example this feature lets customers add an offset to the MEDs received from a particular peer. This feature provides the ability to add or subtract values from : o Metric o Preference o Tag o Color o Local-preference Any place you can set these items, you can now add or subtract relative amounts too, so that values behave like gauges with a minimum and a maximum.
allow the selection of the nexthop LSP based on route attributes like community and as -path. This feature gives the user the flexibility to choose the forwarding nexthop via policy. Junos is providing the user with tools to control which one amongst a set of equal cost nexthops gets installed in the forwarding table. If the desired nexthop LSP is not a viable nexthop for the route Junos falls back to choosing randomly from the ones that are available.
3.2.6 IP Multicast Support The Packet Forwarding Engine features a shared packet memory system that is spread across all interface modules. The shared memory offers the advantage of only having to buffer packets once through the entire system. This is especially useful for multicast forwarding, as packets are written to memory once and can be read from memory many times simultaneously, once for each outgoing next hop. This makes the Juniper routers architecture inherently optimal for multicast support.
MSDP (Multicast Source Discovery Protocol) allows multiple PIM-SM domains to be joined. This is a way to connect multiple PIM-SM domains together. Each PIM-SM domain uses its own independent RP(s) and does not have to depend on RPs in other domains. Some advantages to use MSDP are : § PIM-SM domains can rely on their own RPs only. § Domains with only receivers get data without globally advertising group membership. § Global source state is not required.
3.2.9 IP Tunneling JUNOS supports configuration for a Tunnel Physical Interface Card (PIC) for the Mxxx routers. The Tunnel PIC is a single-wide PIC (that is, occupies one of four PIC slots on an FPC) and provides an OC-12/STM4’s worth of tunneling bandwidth. The Tunnel PIC provides a loopback function that allows packets to be encapsulated and decapsulated. Thus, the PIC has no physical interface. A number of applications for the Mxxx require quick encapsulation and decapsulation of packets.
LSP there is no possibility for parallel paths. However, there could be multiple LSPs configured between the same pair of routers. In this case, either of the algorithms described above could be applied to the operation of the edge LabelSwitching Router (LSR), though once an LSP is chosen by that LSR the packet will take exactly one path through the core. 3.2.
3.3 MPLS for Traffic Engineering Juniper’s architecture for traffic engineering is centered around MPLS. This is an area where Juniper has been proactive through its work with the MPLS and RSVP Working Groups of the IETF as well as with major carriers and ISPs. Juniper’s MPLS support can be viewed as something close to a drop-in replacement for many carriers current static ATM PVCs. Specifically, hop-by-hop paths can be computed off-line based on inputs such as physical topology and a traffic matrix.
selected manually by network operators or automatically by constraint-based routing software. Note that multiple paths can be configured for a particular LSP. If a path is designated as the primary path, then it will be used first to establish the LSP. If the primary path fails then a secondary path is chosen. If the primary path subsequently becomes available then the LSP is moved from the secondary to the primary. JUNOS has a rich set of MPLS features which will continue to get enhanced.
Internet routes but the core is only involved in the IGP and MPLS signaling) and where traffic engineering is not required. 3.3.2 Tunneling LDP LSPs in RSVP LSPs LDP is intended to be used as the label distribution protocol of choice for nontraffic engineered applications. The de-facto standard for label distribution for traffic engineering applications is RSVP (MPLS-RSVP).
3.4 Virtual Private Networks 3.4.1 Layer 2 Virtual Private Networks Today, the Juniper Networks proposal for Virtual Private Networks is based on a Juniper feature set called MPLS Circuit Cross Connect. The Circuit Cross-Connect (CCC) feature enables the transparent connection of two layer 2 circuits at different edges of the network. Because no layer three parsing or lookup is done, CCC supports the transmission of any layer 3 protocols in the packet payload.
CCC for Ethernet 802.1q VLANs is done by setting the encapsulation to VLANCCC on a VLAN basis on a single physical interface. Since Ethernet interfaces in tagged mode can have multiple sub-interfaces, a sub-interface can be either CCC or 'normal'. CCC can be configured only when tagging is enabled. When in normal VLAN mode, all 1024 VLAN IDs can be used but in CCC mode, VLAN IDs from 0 - 511 are reserved for normal VLANs and 512-1023 are reserved for CCC VLANs. 3.4.
While most vendors implement 2547 according to the specification and offer the same value propositions, Juniper Networks leverages current strengths and provide a unique solution. The model of 2547 is based on simple CE routers with most of the routing intelligence residing in the PE routers. In addition to providing basic PE functions, Juniper Networks differentiates its solution by adding QoS and filtering functions that would enable ISPs to sell more services at the edge.
3.4.2.2 VoIP Aware VPNs VoIP is gaining momentum in enterprises, and service providers are planning to introduce it to homes soon. Although the market for VoIP is in the early adopter stage, it is a key planning issue for service providers today. VoIP traffic will be sourced by IP telephones or by the CE router itself. VoIP packets may have IP precedence set at different levels. For example, Cisco IP phones currently use IP precedence level of 5, however, other phones may use different levels.
3.5 Security 3.5.1 Firewall Filters Firewall filters allow you to filter packets based on their contents and to perform an action on packets that match the filter. Depending on the hardware configuration of the router, you can use firewall filters for the following purposes: § § On all routers, you can control the packets destined to or sent by the Routing Engine. On routers equipped with an Internet Processor II ASIC only, you can control packets passing through the router.
3.5.2.2 Filtering Application: Tracing DOS Attacks Denial-of-Service (DOS) attacks are a large concern of ISPs because an attack results in slower network performance, potentially for a large number of customers. A frequently used DOS approach, known as a Smurf Attack, is to spoof the source address of the targeted victim in a series of packets that are sent to a broadcast domain at a proxy site.
filters are useful in protecting the IP services that run on the Routing Engine, such as Telnet, ssh, and BGP, from denial-of-service attacks. The Routing Engine Firewall mechanisms formed the basis for hardware-based packet filtering features for the M20, M40 and M160. Traffic Destined for RE Routing Engine Packet Forwarding Engine RE Firewall Forwarded Traffic The firewall supports a number of match conditions. Each firewall filter consists of one or more “terms”.
With local password authentication, you configure a password for each user allowed to log into the router. RADIUS and TACACS+ are authentication methods for validating users who attempt to access the router using Telnet. They are both distributed client-server systems --the RADIUS and TACACS+ clients run on the router and the server runs on a remote network system. For TACACS+, the JUNOS software supports authentication, but does not support authorization.
Dec 9 18:00:57 lab2 mgd[4578]: UI_CFG_AUDIT_OTHER: user 'root' delete: [protocols bgp group "test group"] "noaggregator-id" Dec 9 18:01:09 lab2 mgd[4578]: UI_CFG_AUDIT_SET: user 'root' set: [protocols bgp group "test group" peer-as] "4444" -> "1234" Dec 9 18:03:58 lab2 mgd[4578]: UI_CFG_AUDIT_SET: user 'root' set: [protocols bgp group "test group" hold-time] -> "37" Page 115 /148
3.6 JUNOS Software specifications The Juniper Networks implementations are industrial strength, full featured, and compliant with all the relevant IETF specifications as well as the deployed base of implementations. The following table lists the specifications support by the JUNOS Internet Software including: § Supported Internet RFC’s § Supported ISO Standards § Supported SONET and SDH Standards Protocol ATM Specification ITU-T Recommendation I.
RFC 2210, The Use of RSVP with IETF Integrated Services RFC 2211, Specification of the Controlled-Load Network Element Service RFC 2215, General Characterization Parameters for Integrated Service Network Elements RFC 2216, Network Element Service Speci fication Template ICMP Extensions for Multiprotocol Label Switching, Internet draft draft-ietfmpls-icmp-00.txt MPLS Label Stack Encoding, Internet draft draft-ietf-mpls-label-encaps04.
ANSI T1.105, Telecommunications - Digital Hierarchy - Optical Interface Rates and Formats Specifications (SONET) ANSI T1.105, Synchronous Optical Network (SONET) Basic Description Including Multiplex Structures, Rates, and Formats ANSI T1.105.02, Synchronous Optical Network (SONET) Payload Mappings ANSI T1.105.06, SONET: Physical Layer Specifications ITU-T Recommendation G.707 (1996), Network node interface for the synchronous digital hierarchy (SDH) ITU-T Recommendation G.
4. AVAILABILITY 4.1 Redundancy Concerns Juniper Networks’ understands the critical importance of product reliability given the point at which the Mxxx will typically be used within a network.
4.1.2 The Fundamental Premise It is useful to recall the fundamental premise that is always made when adding redundancy to a system to make it more reliable. This premise consists of two parts: The first is that when redundant copies of a component are added, there are no significant common-mode failures that affect the redundant copies.
components each of which runs in its own protected environment and interacts with the other components over clean, well-defined interfaces. The second is to provide enough computing power to each component such that it rarely, if ever, runs under stress. The routing system is built on top of a version of Unix that has been custom modified for robust operation under loaded conditions.
4.1.7 Network Level Reliability While these design practices help to make an individual Mxxx more reliable, they do not guarantee it will never fail. What is likely, however, is that with the common hardware failures taken care of the most likely remaining failures will either be due to operator error or to software bugs. The best way to provide network-level reliability is to use loosely coupled redundant Mxxx units in the network and route around failures when they do occur.
connection is broken, the user can switchover mastership by typing the “switchover” command. (More information on switching over below.) If the master RE is hot-swapped out of the system, the backup RE will take over the control of the system as the new master RE. Again, once an RE becomes master, it resets the switch plane and downloads its own version of the microkernel to the PFE components.
image is unstable, the user can issue a second switchover command to revert back to the original master. 4.2.3 Redundant System and Switching Board The M20 supports a redundant System and Switch Board (SSB), that has been implemented is a cold standby, “spare-in-the-box, automatic fail-over” model. SSB redundancy gives providers the option to deploy the M20 with extra protection against switch fabric failure.
SSB Hotplug If the user inserts an SSB while the other SSB is the master, then the switchover will not occur whether or not the redundancy setting has been configured. The switch-over event will only occur if there is a switch-over condition as described above. A syslog entry is generated for each hotplug event so that the provider has a record of what was added or removed and when. 4.2.4 Redundant power supplies The Mxxx have redundant power supplies.
sections of the software. In addition, having clean software interfaces between modules facilitates software development and maintenance, enabling faster customer response and delivery of new features. Other fail-over capabilities supported are in context of Circuit or Router failure: 4.3.2 Automatic Protection Switching (APS) APS is used by SONET add/drop multiplexors (ADMs) to protect against circuit failures. APS is commonly used to protect against failures between the ADM and a router.
ATM-A OC3 544 1058 ATM- OC3A SMF PIC 464 769 ATM- OC3A MMF PIC 597 985 ATM-A OC12 535 1029 OC12-1B SMF ATM PIC 815 1331 OC12-1 MMF ATM PIC 1055 1709 DS3-2-A PIC 559 860 DS3-2-B PIC Gigabit Ethernet Module LX 866 583 1201 1112 Gigabit Ethernet Module SX 656 1198 Predicted System MTBF Component MTBF in (khrs) at 40°° C MTBF in (khrs) at 25°° C M20 chassis only 108 198 M20 chassis with SSB M40 chassis only 77 108 136 198 M40 chassis with SCB 77 136 OC3 POS Interface 46
OC3 POS SMF OC3B PIC 643 1078 0.9999627 0.9999813 Chassis System 64 114 0.9996251 0.9998125 OC3 POS MMF OC3A PIC 597 985 0.9999598 0.9999799 OC3 POS MMF OC3B PIC 931 1555 0.9999742 0.9999871 OC3 ATM A 544 1058 0.9999559 0.9999779 OC12-1 SMF POS 707 1158 0.9999661 0.9999830 OC12-1 MMF POS 881 1434 0.9999728 0.9999864 ATM-A OC12 535 1029 0.9999551 0.9999776 OC12-1-B SMF AT M PIC 815 1331 0.9999706 0.9999853 OC12-1 MMF ATM PIC 1055 1709 0.9999773 0.
NOTES: The following systems MTBFs were provided by the supplier: Power Supply, Fan, and Routing Engine. * Power supplies, Fan Trays, MCS, and REs are fully redundant: 1 to 1. One SFM can support the system wit h reduced bandwidth; hence, 1:4 active redundancy. ** Predicted measure of the degree to which a system is in an operable state at any time (MTTR : Mean Time To Repair).
ATM A 544 1058 0.9999559 0.9999779 OC3A PIC 597 985 0.9999598 0.9999799 Chassis System 64 114 0.9996251 0.9998125 SYSTEM RELIABILITY 32 56 0.9992413 0.9996205 OC12-1 SMF POS SYSTEM RELIABILITY ANALYSIS Chassis System FPC-- 1 FPC OC12 SMF Xcvr MTBF (khrs) ** 40C 25C Availability (At 40C) MTTR = 24hrs MTTR = 12hrs FPC-1 (CPU, 4SRAM, 8DRAM) 80 143 0.9997001 0.9998500 OC12-1 SMF POS 707 1158 0.9999661 0.9999830 Chassis System 64 114 0.9996251 0.
SYSTEM RELIABILITY 33 59 0.9992800 0.9996399 LX GIGABIT ETHERNET V2 SYSTEM RELIABILITY ANALYSIS Chassis System FPC -1 LX GigEther 40C MTBF (khrs) ** 25C Availability (At 40C) MTTR = 24hrs MTTR = 12hrs FPC-1 (CPU, 4SRAM, 8DRAM) 80 143 0.9997001 0.9998500 LX Gigabit Ethernet Card 578 1099 0.9999585 0.9999792 Chassis System 64 114 0.9996251 0.9998125 SYSTEM RELIABILITY 33 60 0.9992840 0.
5. MANAGEABILITY 5.1 5.1.1 Configuration and management Front Panel and Craft Interface The M40 has a craft interface on the front panel. The display panel offers the following capabilities: § Four-line backlit LCD display for the entire system, with six navigation buttons. The display has an adjustable contrast and viewing angle. § System LEDs and buttons: § Two LEDs per NIC module slot (Green OK and Red Fail) and one off-line button. § Two big Alarm LEDs (Red, Orange) plus an Alarm Cutoff button.
Operators can configure the M20/M40 by entering configuration mode and creating a hierarchy of configuration statements. A configuration can be created on the router, interactively, by using the CLI or by loading a text (ASCII) file containing the statement hierarchy that was created earlier. All properties of the JUNOS software can be configured, including: interfaces, general routing information, routing protocols, user access, as well as a number of hardware properties.
§ Reboot the router; either by power-cycling it or by issuing the request system reboot command from the CLI. § When the router finishes booting, you are prompted for the terminal type: § These are the predefined terminal types available to sysinstall when running stand-alone. Please choose the closest match for your particular terminal. 1 ...................... Standard ANSI terminal. 2 ...................... VT100 or compatible terminal. 3 ...................... FreeBSD system console (color). 4 ....
shall maintain a "supported release" of software on all of its systems at all times. A supported release is defined as a version that is no more than three releases old or eighteen months old, whichever is less. 5.5 Fault Monitoring There are a variety of mechanisms for monitoring fault conditions on the M20/M40. One mechanism is to report state via the red or yellow alarm indication on the craft panel interface. A second mechanism is extensive logging that is done for processes in the system.
Loss of frame Loss of signal Phase locked loop out of lock Yellow alarm Ethernet 5.5.3 Management Ethernet disconnected. Syslog In JUNOS, you can turn on debugging at different levels using syslog and tracing operations. System logging operations use a syslog-like mechanism to record systemwide, high-level operations, such as interfaces going up or down and users logging into or out of the router.
OAM VC-AIS (alarm indication signal) and VC-RDI (remote defect indication) defect indication cells are used for identifying and reporting VC defects end-toend. You can also configure the OAM F5 loopback cell threshold on VCs, which is the minimum number of consecutive OAM F5 loopback cells received before declaring that a VC is up or lost before declaring that a VC is down. 5.5.4.
5.6 Statistical Analysis The Internet Processor II supports sampling that is randomized around a configurable sampling rate. Sampling of "packet trains" is supported, meaning that users can configure the number of consecutive packets to sample at any one time. Additionally, filters can be set to select which packets are candidates for sampling. For example, a filter can be applied to sample a percentage of HTTP traffic flowing through a particular interface. 5.6.
and deployment. ISP peering decisions are an example of where sampling information is useful. For example, ISP1 can use sampling to analyze the traffic received on its link from ISP2 in order to determine how much of the traffic on the link originated from a third ISP, ISP3. If the volume of traffic from ISP3 is high enough, then a direct peering link to ISP3 may be justified to improve efficiency and response time. ISP2 might be interested in the same information for its own business reasons.
6. INTEROPERABILITY Internet Interoperability : The Juniper Networks routing protocol implementations have demonstrated their character and stability by successfully running in several ISP backbones for the past year.
7.
Interface Tested: OC3 POS Test Date: 5/26/99 router router router router input output input bps output bps input pps output pps ppp ohead ppp ohead 48bits/pkt 48bits/pkt Packet Size input output hdlc ohead hdlc ohead 8bits/pkt 8bits/pkt 48 127408624 127408624 398151 398151 19111248 19111248 3185208 3185208 64 129978704 129978336 353202 353202 16953696 16953696 2825616 2825616 120 140139840 140139840 171740 171740 8243520 8243520 1373920 1373920 128 140798240 1407
Interface Tested: OC12 POS Test Date: 5/26/99 router router router router input output input bps output bps input pps output pps ppp ohead ppp ohead 48bits/pkt 48bits/pkt 8bits/pkt 8bits/pkt Packet Size input output hdlc ohead hdlc ohead 48 509596896 509794664 1592491 1593109 76439568 76469232 12739928 12744872 64 519715208 519715576 1412271 1412270 67789008 67788960 11298168 11298160 120 561928048 561928048 662651 662651 31807248 31807248 5301208 5301208 128 56
Interface Tested: OC48 POS Test Date: 5/26/99 router router router router input output input bps output bps input pps output pps ppp ohead ppp ohead 48bits/pkt 48bits/pkt 8bits/pkt 8bits/pkt Packet Size input output hdlc ohead hdlc ohead 48 1816965440 1817297600 5678018 5679055 272544864 272594640 45424144 45432440 64 2014021560 2014143232 5472884 5473215 262698432 262714320 43783072 43785720 120 2242243152 2242228464 2747848 2747829 131896704 131895792 21982784 2
Interface Tested: OC3 ATM Test Date: 5/26/99 router router router router input bps output bps input pps output pps Packet Size input output input bps output bps # of cells # of cells without without per packet per packet sonet ohead sonet ohead 48 56512320 56512000 176601 176600 2 2 149757648 149756800 64 64988800 64988800 176600 176600 2 2 149756800 149756800 120 96070944 96070128 117734 117733 3 3 149757648 149756376 128 103605920 103605920 117734 117734 3
Interface Tested: OC12 ATM Test Date: 5/26/99 router router router router input bps output bps input pps output pps Packet Size input output input bps output bps # of cells # of cells without without per packet per packet sonet ohead sonet ohead 48 213200320 213190400 666251 666220 2 2 564980848 564954560 64 245178528 245161232 666246 666199 2 2 564976608 564936752 120 379648896 379652160 465256 465260 3 3 591805632 591810720 128 408734480 408760000 464471 464500
Interface Tested: DS3 Test Date: 5/26/99 router router router router input input bps output bps input pps output pps ppp ohead ppp ohead hdlc ohead hdlc ohead 48bits/pkt 48bits/pkt Packet Size output input 8bits/pkt output 8bits/pkt 48 37327040 37327040 116647 116647 5599056 5599056 933176 933176 64 38100880 38100880 103535 103535 4969680 4969680 828280 828280 120 41227584 41228400 50524 50525 2425152 2425200 404192 404200 128 41431280 41431280 47081 470
Interface Tested: Gigabit Ethernet Test Date: 5/26/99 router router router router input bps output bps input pps output pps input Packet Size output input output ethernet ethernet preamble preamble overhead overhead overhead overhead 48 476563200 476575360 1489260 1489298 214453440 214458912 95312640 95315072 64 547603504 547612336 1488053 1488077 214279632 214283088 95235392 95236928 120 728553360 728565600 892835 892850 128568240 128570400 57141440 57142400 128 743
