User's Manual

Page 49 of 83

A Carrier Corp. Company

PART NUMBER T82002163

REV A

Functional Description

The Memory Stick system, depicted in Figure 17-1, consists of the memory stick host controller

and an attached Memory Stick card.

Figure 17-1. Memory Stick System Block Diagram

The memory stick host controller interfaces with the Memory Stick using a 32-bit internal

application interface. It allows:

•

Sending of transfer protocol commands (TPCs) to the Memory Stick using the MSHC

Command register.

•

Data transfer using the two separate receive (RX) and transmit (TX) FIFOs (this data can be

transferred using polling, interrupts to the processor, or DMA).

•

Responding directly to Memory Stick interrupts by issuing a predefined command, the

AutoCommand (ACD).

•

Placing the card into a low-power mode.

Interrupts

The memory stick host controller generates a single interrupt to the interrupt controller. The cause

of the interrupt can be determined by reading the Interrupt and Status register.

Status bits in this register indicate which event caused the interrupt to be generated. Interrupts can

be disabled (either individually or in total) by setting bits in the Interrupt Enable register.

To process an interrupt, MSINTEN[INTEN] must be set, and the enable bit for the specific

interrupt in register MSINTEN must be set.

It is possible for multiple secondary interrupts to occur if more than one MSINTEN register bit

besides INTEN are set. To determine the specific cause of the interrupt, read the Interrupt and

Status register, MSINT. To handle more than one interrupt at a time, set MSINTEN[INTEN] and

the specific MSINTEN interrupt enable bits.

Memory Stick Insertion and Removal

The nMSINS signal indicates the insertion and removal of a Memory Stick. nMSINS is connected

to the interrupt controller, but not to the memory stick host controller. Thus, the interrupt controller

must be programmed to generate an nMSINS interrupt.