User's Manual

Page 45 of 83

A Carrier Corp. Company

PART NUMBER T82002163

REV A

discussed in detail.

Note: The processor does not provide direct connection to or control of the USB Vbus.

Figure 12-15. USB OTG Configurations

On-Chip OTG Transceiver Operation

The USB host port 2 transceiver is designed in accordance with the Pull-up/Pull-down Resistors

Engineering Change Notice to the USB 2.0 Specification to provide on-chip resistors and OTGcompliant

transceiver operation. The USB host controller port 2 multiplexor is a bidirectional I/O

multiplexor that connects to the USB host port 2 transceiver and the single-ended I/O through the

GPIO. The port 2 multiplexor provides an interface that allows the UDC port or UHC port 2 to

connect to the UHC port 2 transceiver for direct bidirectional connection to the USB. The port 2

multiplexor also provides an interface that allows the UDC port, UHC port 2, and the UHC port 3

to connect to single-ended I/O through the GPIOs.

The OTG transceiver contains two pull-up resistors and one pull-down resistor on each D+ and D–

that can be enabled using the USB Port 2 Output Control Register (UP2OCR) pull-up/pull-down

enable bits (DPPUBE, DMPUBE, DPPUE, DMPUE, DPPDE, DMPDE). Figure 12-16 illustrates

the on-chip host port 2 transceiver pad with the pull-up and pull-down resistors.

• Enable SW3 for both D+ and D– when host port 2 is being used for USB host controller data.

• Enable SW1 on the D+ pad and disable SW1 on the D– pad when host port 2 is being used for

USB device controller data.

• Disable SW2 on the D+ and D– pads when host port 2 is being used for USB device controller

data.

• SW2 is enabled and disabled by hardware when the UDC is idle and receiving data from an

upstream device as specified in the Pull-up/Pull-down Resistors Engineering Change Notice

to the USB 2.0 Specification. Table 12-9 lists the switch settings used for the USB host and

USB device controller I/O.