User's Manual

Page 44 of 83

A Carrier Corp. Company

PART NUMBER T82002163

REV A

remote wake-up feature of the UDC, after the UDC has entered the suspend state, sending a wakeup

signal to the USB host controller is performed by setting UDCCR[UDR]. Doing so forces the

UDC to drive a non-idle state (K state) onto the USB for 3 milliseconds without further user

intervention. The UDC hardware then clears UDCCR[UDR]. The UDC waits for the resume signal

to be reflected back to it by the USB host controller, and when the resume state is detected on the

USB, if the resume interrupt is enabled, an interrupt is sent to the processor.

The USB host controller can wake up the UDC by driving the non-idle state (K state) either by

driving a resume or USB reset onto the USB. When the UDC pads detect this non-idle state on the

USB, they signal the processor clock manager module to start the 48-MHz clock to the UDC, and

(if the resume interrupt is enabled) an interrupt is sent to the processor. Software must take the

appropriate action to resume activity.

Sleep Mode Operation

If the UDC has entered the suspend state before the PXA27x processor is in sleep mode, the UDC

pins USBC_P and USBC_N are used to detect the resume state on the USB and resume operation

while the processor is in sleep mode. If the USB host controller tries to access the UDC when the

processor is in sleep mode, the USBC_P and USBC_N pins detect the resume state and signal the

processor to begin the wake-up sequence. The UDC will have lost all state information and the

UDC Configuration registers must be reloaded prior to setting UDCCR[UDE]. The USB host

controller must issue a USB reset and re-enumerate the UDC.

If the UDC has been disconnected from the USB and the processor is in sleep mode, a GPIO pin

must be programmed to detect connection to the USB and to signal the processor to begin the

wake-up sequence. The GPIO pin must be connected through a level-shifter to the USB power

signal to detect connect/disconnect to the USB. The UDC will have lost all state information and

users must load the UDC Configuration register and enable the UDC before the UDC is ready for

USB operation.

USB On-The-Go Operation

The processor USB device and host controllers can be used to provide A- and B-device On-The-Go

(OTG) operation as specified in the On-The-Go Supplement to the USB 2.0 Specification. The onchip

OTG transceivers provide on-chip pull-up and pull-down resistors as specified in the Pull-up/

Pull-down Engineering Change Notice to the USB 2.0 Specification. OTG operation requires user

intervention but interrupts are provided to notify the user of OTG activities including Vbus

changes, session detection, and OTG ID changes. The user must use these interrupts along with the

OTG control and status registers to operate as an OTG device. The UDC OTG support includes the

following:

• Decoding of SET_FEATURE commands with OTG specific selector values

• Control for on-chip OTG transceiver with multiplexing between UDC and USB host controller

(UHC) port 2

• Control for multiplexing between UDC, UHC port 2 and UHC port 3 data through GPIOs

• Control, status and interrupt registers for interfacing to off-chip OTG transceivers

• Control, status and interrupt registers for interfacing to off-chip charge pump devices

• OTG ID support

Figure 12-15 shows each of the configurations provided to support OTG operation. Each of these is