User's Manual

ManualsBrandsSensitech ManualsElectronicsPART 15 CLASS B COMPUTING DEVICE PERIPHERAL

Page 43 of 83

A Carrier Corp. Company

PART NUMBER T82002163

REV A

endpoint, the FIFO Service (FS) and Packet Complete (PC) bits in the Endpoint Control/Status

The Byte Count register of each endpoint indicates the number of data bytes that need to be

unloaded from the buffer. As data is read from the FIFO memory using the Data register, the

corresponding Byte Count register value is decremented to indicate the number of bytes remaining

in the buffer. When all of the data has been unloaded from the FIFO memory, the FS and Buffer

Not Empty/Buffer Not Full (BNE/BNF) bits in the Control/Status register and the Byte Count (BC)

in the Byte Count register are cleared by the UDC to indicate the current buffer is empty. After

reading all of the data from the endpoint buffer, software must clear the PC bit in the corresponding

Control/Status register.

If an OUT endpoint has double-buffering enabled, the Control/Status and Byte Count registers

provide the status of the endpoint buffer that is currently active. The FS, PC, and BNE/BNF bits in

the Endpoint Control/Status register are set when the first buffer has received a complete data

packet. The short-packet (SP) bit indicates a packet smaller than the maximum packet size has been

received and is ready for unloading, or has been loaded and is ready for transmission. The Data

hold the status of the first buffer until software clears the PC bit in the Control/Status register.

As the data is read from the first receive buffer, the value in the Byte Count register is decremented

and indicates the number of data bytes that still need to be read from the first buffer in the FIFO

memory. When all of the data in the first buffer has been read, the Byte Count register and the

BNE/BNF bit in the Control/Status register are cleared. If a second packet is received before all of

the data has been read from the first buffer, the FS bit continues to be set after the first buffer is

been read, but the second packet of data does not set the PC bit until after software has cleared the

PC bit.

The status of the second buffer cannot be determined until the PC bit is cleared. The PC bit must be

set to update the Control/Status and Byte Count registers with the status of the second buffer. If the

PC bit is set before reading all of the data in the first receive buffer, the data in the first receive

buffer is lost.

If the second buffer has received a complete data packet, the PC bit is again set to indicate that the

endpoint FIFO has data ready to be unloaded, and the BNE/BNF and Byte Count registers indicate

the amount of data present in the second buffer. At this point, the Data register unloads data from

the second buffer. The Control/Status and Byte Count registers continue to hold the status of the

second buffer until software again clears the PC bit. Only after all of the data has been read from

the second buffer must the PC bit be set. Doing so updates the Control/Status and Byte Count

registers to reflect the status of the first buffer.

Suspend and Resume

If idle persists on the USB for more than 3 ms, the UDC detects the suspend state, and (if the

suspend interrupt is enabled) an interrupt is sent to the processor. When the UDC enters the

suspend state, the processor stops the 48-MHz clock to the UDC and enables the UDC pins

USBC_P and USBC_N to detect the resume state. If the processor does not enter sleep mode, the

state of the UDC is preserved and is ready for resume detection.

Note: The presence of SOF packets prevents the UDC from entering suspend mode.

The UDC can exit suspend in three ways:

• Resume initiated by the UDC

• Resume initiated by the USB host controller

• USB reset

If the USB host controller has executed the SET_FEATURE command and enabled the device