User's Manual

© SENSITECH INC. CONFIDENTIAL – CONTROLLED DOCUMENT Page 42 of 83
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PART NUMBER T82002163
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are 53 sources for this interrupt. Each of the 24 endpoints (0 and A–X) has two interrupts: packet
complete and FIFO error. In addition, the UDC has five interrupts that can be generated based on
USB activity. The interrupt sources are shown in the UDC Interrupt Status registers, which must be
read to determine the cause of the interrupt being generated. In addition, USB activity can be
determined by reading the UDC Interrupt Status registers. If polling is used, the Endpoint Control/
Status registers can be read to determine activity on the USB.
The UDC Interrupt Control registers contain interrupt-enable bits that enable the generation of the
UDC interrupt. When an interruptible event occurs, the appropriate status bit in the Endpoint
Control/Status register is set, and if the corresponding interrupt-enable bit in the Interrupt Control
register is set, then the appropriate bit in the Interrupt Status register is set and an interrupt is
generated. An interrupt is cleared by setting the appropriate bit in the Interrupt Status registers
Endpoint 0 is the only control endpoint and the only bidirectional endpoint in the UDC, and has
characteristics different from the programmable endpoints A–X. Key characteristics of endpoint 0
include the following:
• Control/Status, Byte Count, and Data registers
• Configuration is fixed and does not use a configuration register
• Enabled for every USB configuration and interface
• Bidirectional endpoint with 32 bytes of USB data-storage space allocated in the endpoint
memory: 16 bytes of FIFO memory are used for IN data and 16 bytes are used for OUT data
• USB data space is not double-buffered.
• Only endpoint configured and available for USB operation after USB reset, and before the
USB host controller has enumerated the UDC
The Endpoint 0 Control/Status and Byte Count registers provide the status of the endpoint 0 IN and
OUT buffers. The Receive FIFO Not Empty bit (UDCCSR0[RNE]) and OUT Packet Complete bit
(UDCCSR0[OPC]) are set when a complete data packet has been received from the USB host
controller. If the packet is part of a SETUP transaction, the Setup Active bit (UDCCSR0[SA]) is
also set. The endpoint 0 transmit FIFO is flushed by the UDC after receiving an OUT data packet
from the USB host controller. The Byte Count register (UDCBCR0) indicates the number of bytes
of data that need to be unloaded from the receive buffer. As data is read from the endpoint 0 receive
buffer using the Endpoint 0 Data register UDCDR0, the Byte Count register value is decremented
to indicate the number of bytes remaining in the buffer. When all of the data has been unloaded
from the receive buffer, UDCCSR0[RNE] is cleared by the UDC to indicate the receive buffer is
empty. After reading all of the data from the endpoint 0 receive buffer, software must clear
UDCCSR0[OPC] to enable the buffer to receive another USB data packet.
Loading a maximum packet size of 16 bytes into the endpoint 0 transmit FIFO automatically sets
UDCCSR0[IPR]. If less than 16 bytes are loaded into the endpoint 0 transmit FIFO,
UDCCSR0[IPR] must be explicitly set to indicate a complete packet has been loaded. When the
data has been transmitted to the USB host controller, the UDC clears UDCCSR0[IPR] to indicate
the packet has been sent
Each of the 23 programmable endpoints, referred to as endpoints A–X, has a Configuration
register, Control/Status register, Byte Count register, and a Data register. The Configuration
registers set the configuration, interface, alternate setting and endpoint numbers, and maximum
packet size, as well as enable double-buffering for each endpoint. The Configuration registers can
be written only when the UDC is not enabled (UDCCR[UDE] is clear). When UDCCR[UDE] is
set, the endpoint configurations are loaded into the USB interface block and are set to read-only
access.
The Control/Status, Byte Count, and Data registers control the operation of each endpoint after
enumeration. If an endpoint has double-buffering disabled, the Control/Status and Byte Count
registers provide the status of the endpoint buffer. If the endpoint is configured as an OUT