User's Manual

© SENSITECH INC. CONFIDENTIAL – CONTROLLED DOCUMENT Page 41 of 83
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PART NUMBER T82002163
REV A
Operation
The UDC consists of four major components: the peripheral bus interface, endpoint memory,
endpoint control, and USB interface. The peripheral bus interface contains the UDC control and
status registers for the endpoint configuration data and provides the interface between the PXA27x
processor and the USB data. The endpoint memory is a 4-Kbyte SRAM used for USB endpoint
data storage. It has 32 bytes dedicated to endpoint 0, allowing the remainder of its memory to be
allocated to any of the 23 programmable endpoints. The endpoint control and USB interface blocks
provide the USB functionality. Figure 12-2 is a block diagram of the USB client controller and its
dedicated I/O.
Figure 12-2. USB Client Controller Block Diagram
Peripheral Bus Interface and Control/Status Registers
The UDC is a slave peripheral device that is connected to the internal peripheral bus. All userinitiated
accesses to the UDC registers and endpoint memory are completed using the internal
peripheral bus. The control and status registers include registers for frame-number storage, UDC
top-level control and status, interrupt control and status, endpoint control, status, and data transfer.
The UDC Control register (UDCCR) provides control and status of internal UDC functions. The
UDCCR status bits indicate the current USB configuration, interface, and alternate interface setting
numbers assigned the UDC by the USB host controller. The UDCCR also contains a status bit to
indicate if the UDC is actively communicating on the USB, and a status bit to indicate an unusable
endpoint memory configuration. The UDCCR also allows selection of UDC enable for USB
operation, UDC resume, and endpoint memory configuration control
Either processor interrupts or polling can be used to determine whether USB activity occurs. The
Frame Number register (UDCFNR) holds the frame number contained in the last received start-offrame
(SOF) packet.
Although the UDC can generate only a single interrupt to the processor’s interrupt controller, there