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ManualsBrandsSensitech ManualsElectronicsPART 15 CLASS B COMPUTING DEVICE PERIPHERAL
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register before it goes to the pin.
When the UART unit is disabled, the transmitter or receiver finishes the current byte and stops
transmitting or receiving more data. Data in the FIFO is not cleared, and transmission resumes
when the UART is enabled.
USB Client Controller:
Overview
The UDC supports 24 endpoints (endpoint 0 plus 23 programmable endpoints). The UDC is a USB
Revision 1.1-compliant, full-speed device that operates half-duplex at a baud rate of 12 Mbps (as a
slave only, not as a host or hub controller).
The serial information transmitted and received by the USB client controller contains layers of
communications protocols as defined by Universal Serial Bus Specification, Revision 1.1, the most
basic of which are fields.
• USB fields include: sync, packet identifier, address, endpoint, frame number, data, and CRC.
Fields are used to produce packets. Depending on the packet function, a different combination
and number of fields can be used.
• Packet types include: token, start of frame, data, and handshake. Packets are assembled into
groups to produce transfers, transactions, and frames.
• Transfers fall into four groups: bulk, control, interrupt, and isochronous.
• Transactions fall into four groups: IN, OUT, SOF, and SETUP. Data flow is relative to the
USB host controller. IN packets represent data flow from the USB client controller to the host
controller. OUT packets represent data flow from the USB host controller to the client
controller.
Figure 12-1 graphically represents the communications layers in the protocol. See the Universal
Serial Bus Specification, Revision 1.1 for more details on USB protocol.
The UDC uses single-ported memory to support FIFO operations. Bulk, isochronous, and interrupt
endpoint FIFO structures can be double-buffered to enable the endpoint to process one packet
while assembling another. Use either DMA or the Intel XScale® core to fill and empty the FIFOs.
An interrupt, DMA service request, or polling can be used to detect packet receipt.
The USB host controller referenced in this chapter refers to any USB host controller that is
compliant to the Universal Serial Bus Specification, Revision 1.1, including the PXA27x
processor’s internal USB host controller.
Figure 12-1. Communications Protocol Layers in the USB Client Controller