User's Manual

Page 38 of 83

A Carrier Corp. Company

PART NUMBER T82002163

REV A

The receive-data sample counter frequency is 16 times the value of the bit frequency. The 16X

clock is created by the baud-rate generator. Each bit is sampled three times in the middle. Shaded

bits in Figure 10-1 are optional and can be programmed by software.

Each data frame is between 7 and 12 bits long, depending on the size of the data programmed,

whether parity is enabled, and the number of stop bits. A data frame begins by transmitting a start

bit that is represented by a high-to-low transition. The start bit is followed by from 5 to 8 bits of

data that begin with the least significant bit (LSB). The data bits are followed by an optional parity

bit. The parity bit is set if even-parity is enabled and the data byte has an odd number of ones, or if

odd parity is enabled and the data byte has an even number of ones. The data frame ends with 1,

1½, or 2 stop bits, as programmed by software. The stop bits are represented by 1, 1½, or 2

successive bit periods of logic 1.

Each UART has two FIFOs: one transmit and one receive. The transmit FIFO is 64 bytes deep and

8 bits wide. The receive FIFO is 64 bytes deep and 11 bits wide. Three bits are used for tracking

errors.

The UART can use non-return-to-zero (NRZ) coding to represent individual bit values. To enable

NRZ coding, set IER[5]. A bit value of 0b1 is represented by a line transition, and 0b0 is

represented by no line transition. Figure 10-2 shows the data byte 0b0100_1011 in NRZ coding.

The byte’s LSB is transmitted first.

Figure 10-2. Example NRZ Bit Encoding—0b0100_1011

Reset

The UARTs are disabled on reset. To enable a UART, software must program the GPIO registers

(see Section 24, “General-Purpose I/O Controller”), then set IER[UUE]. When the UART is

enabled, the receiver waits for a frame-start bit and the transmitter sends data if it is available in the

Transmit Holding register. Transmit data can be written to the Transmit Holding register before the

UART unit is enabled. In FIFO mode, data is transmitted from the FIFO to the Transmit Holding