User's Manual

Page 34 of 83

A Carrier Corp. Company

PART NUMBER T82002163

REV A

For both reads and writes from and to VLIO, clearing DCMDx[INCSRCADDR] and

DCMDx[INCTRGADDR] causes the source and target addresses not to be incremented to the

VLIO interface, which allows port-type VLIO chips to interface with the processor. The only valid

memory types for this DMA mode are VLIO and PC Card/CompactFlash devices.

For writes to VLIO, if all byte enables are turned off (masking out the data, DQM = 0b1111), then

the write enable is suppressed (nPWE = 1) for this write-beat to VLIO. This suppression can cause

a period when nCS is asserted but neither nOE nor nPWE is asserted, which would happen if there

is a write of one beat to VLIO with all byte enables turned off. In this case, the memory controller

ignores the RDY signal. The RDY signal must not be asserted late if it is to still be asserted, which

could interfere with any following transfers. If the VLIO device does not see an nOE or a nPWE, it

must not change the state of RDY, keeping it either asserted or de-asserted.

With the exception of the case above, and when entering a frequency change, the memory

controller indefinitely waits for the RDY signal to be asserted, which can hang the system if the

external VLIO is not responding. To prevent indefinite hangs, set the watchdog timer when starting

a VLIO transfer; a watchdog reset occurs if no response is received from the VLIO device.

Figure 6-5. Variable-Latency I/O Diagram

UARTs

This chapter describes the universal asynchronous receiver/transmitter (UART) serial ports

included in the PXA27x processor. The serial ports are controlled using direct-memory access

(DMA) or programmed I/O. The PXA27x processor has three UARTs: full-function (FFUART),

Bluetooth (BTUART), and standard (STUART). All UARTs use the same programming model.

Overview

Each serial port contains a UART and a slow infrared-transmit encoder and receive decoder that

conform to the IrDA serial-infrared specification.1

Each UART performs serial-to-parallel conversion on data characters received from a peripheral

device or a modem and parallel-to-serial conversion on data characters received from the

processor. The processor can read a UART’s complete status during functional operation. Status

information includes the type and condition of transfer operations and error conditions (parity,

overrun, framing, or break interrupt) associated with the UART.

Each serial port operates in either FIFO or non-FIFO mode. In FIFO mode, a 64-byte transmit

FIFO holds data from the processor until it is transmitted on the serial link, and a 64-byte receive