User's Manual

Page 33 of 83

A Carrier Corp. Company

PART NUMBER T82002163

REV A

MSCx[RDF] defines the latency (in memory clock cycles) for the first and all subsequent data

beats from non-burst ROMs and the first data beat from a burst ROM. The value of MSCx[RDN]

defines the latency for the burst data beats after the first for burst ROMs. Specifying the

MSCx[RRR] value allows a delay on the next access to a different memory space to allow time for

the current ROM to three-state the data bus. MSCx[RRR] must be programmed with the maximum

TOFF value divided by two, as specified by the ROM manufacturer.

MSC0<15:0> is selected when the address space corresponding to nCS<0> is accessed.

SRAM Interface Overview

The processor provides a 16- or 32-bit synchronous SRAM interface that uses the DQM pins for

byte enables on writes. Bits nCS<5:0> select the SRAM bank to be used. nOE is asserted on reads

and nWE is asserted on writes. Address bits MA<25:0> allow up to 64 Mbytes of SRAM per bank

to be addressed.

The RDF fields in the MSCx registers define the latencies for a read access. The MSCx[RDN] field

controls the nWE low time during a write cycle. MSCx[RRR] is defined as the minimum time from

nCS de-assertion to the beginning of a read or write access of any memory bank

Any DMA mode that does not increment the address is not supported for SRAM reads or writes.

DCMDx[INCSRCADDR] and DCMDx[INCTRGADDR] clear cause the address not to be

incremented. This DMA mode is not supported for SRAM. The only valid memory types for this

mode are VLIO and PC Card/CompactFlash devices.

Variable-Latency I/O Interface Overview

When a companion chip is used as a VLIO device, its functionality is similar to that of an SRAM

with the additional ability to insert a variable number of wait states through the RDY pin. VLIO

can be used in the memory space for any of the six static memory locations (nCS<5:0>) by

programming the corresponding MSCx[RTx] to 0b100.

13:11 FREQUENCY CONFIGURATION

0b010 -> Code 2 (CAS latency 3)

0b011 -> Code 3 (CAS latency 4)

0b100 -> Code 4 (CAS latency 5)

0b101 -> Code 5 (CAS latency 6)

0b110 -> Code 6 (CAS latency 7)

Choose this value based on the “AC Characteristics—Read-Only

Operation” section of the flash-memory device data sheet.

14 reserved 0b0

15 READ MODE 0b0 = Synchronous operation

0b1 = Asynchronous operation

Table 6-12. Sample Read Programming Values for Synchronous Flash Memory

Bits Field Name Value to Program

Memory Controller

VLIO read accesses differ from SRAM read accesses in that nOE toggles for each beat of a burst.

The first nOE assertion occurs two CLK_MEM cycles after the chip select, nCSx, is asserted. For

VLIO writes, nPWE is used instead of nWE, which allows SDRAM refreshes to execute while

performing the VLIO transfers.