User's Manual
© SENSITECH INC. CONFIDENTIAL – CONTROLLED DOCUMENT
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PART NUMBER T82002163
REV A
Synchronous Flash Memory
This section describes how to interface with synchronous flash memory. Synchronous flashmemory
operation resets to asynchronous mode (page mode for reads and asynchronous singleword
writes). The only way the system can enter synchronous mode (burst-timing synchronous
reads and asynchronous single-word writes) is through the Read Configuration register (RCR).
Therefore, at boot time, synchronous flash memory operates the same as asynchronous boot ROM.
Table 6-12 shows sample programming values for the RCR Synchronous Flash Memory register to
ensure proper operation of synchronous flash memory.
Use the values in Table 6-12 as a reference only. Consult the data sheet for the actual part being
used. Determine the frequency-configuration code based on the CLK-to-output delay, the CLK
period, and the nADV-to-output delay timing parameters for the flash device.
Table 6-12. Sample Read Programming Values for Synchronous Flash Memory (Sheet 1 of 2)
Bits Field Name
Value to Program†
2:0 BURST LENGTH 0b010 = 8-word burst
5:3 reserved 0b000
6 CLOCK CONFIGURATION
0b1 = Use rising edge of clock
7 BURST SEQUENCE
0b1 = Linear burst order (Intel burst order is not
supported)
8 WAIT CONFIGURATION
Not applicable—The processor ignores nWAIT from
the flash device.
9
DATA OUTPUT
CONFIGURATION
0b0 = Hold data for one clock
10 reserved 0b0
†
for configuration register
Table 6-12. Sample Read Programming Values for Synchronous Flash Memory (Sheet 2 of 2)
Bits Field Name
Value to Program†
0b010 -> Code 2 (CAS latency 3)
0b011 -> Code 3 (CAS latency 4)
0b100 -> Code 4 (CAS latency 5)
13:11
FREQUENCY
CONFIGURATION
0b101 -> Code 5 (CAS latency 6)
0b110 -> Code 6 (CAS latency 7)
Choose this value based on the “AC Characteristics—
Read-Only
Operation” section of the flash-memory device data
sheet.
14 reserved 0b0
15 READ MODE
0b0 = Synchronous operation 0b1 = Asynchronous
operation
†
for configuration register
ROM Interface
The processor provides programmable timing for both burst and non-burst ROMs. The value of