User's Manual

© SENSITECH INC. CONFIDENTIAL – CONTROLLED DOCUMENT Page 31 of 83
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PART NUMBER T82002163
REV A
• Burst-of-eight ROM or flash memory
The MSCx[RBWx] fields specify the bus width for the memory space selected by nCS<5:0>. If a
16-bit bus width is specified, transactions occur across data pins MD<15:0>. Use the BOOT_SEL
pin or SXCNFG register to configure nCS<3:0> for synchronous static memory.
Asynchronous Flash Memory Interface
The MSCx[RDFx] bit fields define the latency for each read access of non-burst flash memory or
the first read access of burst flash memory. The same bit field also controls the nWE de-assertion
time during a write cycle to flash memory. The MSCx[RDN] field controls subsequent read access
times to burst flash memory. The MSCx[RRR] bit field calculates the minimum period from the
nCS signal de-assertion following a read or write and before the start of the read from a different
memory.
The following requirements apply to reads from flash memory:
• Because flash memory defaults to read-array mode, burst reads from it are permitted, which
allows instruction caching and burst reads (DMA and USB host) from flash memory.
• Some areas of flash memory might not permit burst reads. When attempting to read from these
areas, do not attempt burst reads. Consult the flash-memory data sheet for more information.
Table 6-10. 32-Bit Byte Address Bits MA<1:0> for Writes Based on DQM<3:0>
Transaction DQM<3:0> MA<1:0>
Word 0b0000 0b00
Byte 0 0b1110 0b00
Byte 1 0b1101 0b01
Byte 2 0b1011 0b10
Byte 3 0b0111 0b11
Lower half word 0b1100 0b00
Upper half word 0b0011 0b10
Table 6-11. 16-Bit Byte Address Bit MA<0> for Writes Based on DQM<1:0>
Transaction DQM<1:0> MA<0>
Half word 0b00 0b0
Byte 0 0b10 0b0
Byte 1 0b01 0b1
Memory Controller
• Software must partition commands and data, then write the commands to flash memory before
a read. The memory controller does not insert any commands before flash-memory reads.
The following requirements apply to writes to flash memory:
• Flash memory space must be uncacheable and unbuffered.
• Burst writes to flash memory do not exist. Writes to flash memory must be exactly the width of
the populated flash devices on the data bus and must be a burst length of one write (for
instance, no byte writes to a 32-bit bus, no word writes to a 16-bit bus, no writes of 2 bytes to a
32-bit bus, no writes of 1 byte to a 16-bit bus). The allowable writes are 2 bytes to a 16-bit bus
and 4 bytes to a 32-bit bus.
• For writes to flash memory, the command and data must be given to the memory controller in
separate write instructions. The first instruction carries the command; the next carries the data.
• Software must partition commands and data and write them to flash memory in the appropriate
sequence. The memory controller does not insert any commands before flash-memory writes.
• Because burst writes to flash memory cannot occur, the DMA controller and USB host
controller must never write to flash memory. Burst writes to flash memory are not performed.