User's Manual

© SENSITECH INC. CONFIDENTIAL – CONTROLLED DOCUMENT Page 30 of 83
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PART NUMBER T82002163
REV A
configurable for the following:
• Non-burst ROM or flash memory
• Burst ROM or flash memory
• SRAM
• VLIO devices
The VLIO interface differs from SRAM in that it allows the use of a data-ready input signal, RDY,
to insert a variable number of memory-cycle wait states. The data bus width for each chip-select
region can be programmed to be 16- or 32-bit. The nCS<3:0> signals are also configurable for
synchronous static memory. The following list describes the use of nOE,
nWE, and nPWE:
• nOE is asserted for all reads.
• nWE is asserted for flash memory and SRAM writes.
• nPWE is asserted for VLIO writes.
For SRAM and VLIO implementations, DQM<3:0> are used for the write byte-enables, where
DQM<3> corresponds to the MSB. The processor supplies 26 bits of byte address for access of up
to 64 Mbytes per chip select. This byte address is sent out on the 26 external address pins. If the
byte address is unimportant for an application, the lower bit must be truncated for 16-bit systems
and the lower two bits must be truncated for 32-bit systems. For reads, the byte address bits is 0.
For writes, the byte address bits are summarized in Table 6-10 and Table 6-11.
Table 6-10. 32 Bit Byte Address Bits MA <1.0>
for Writes Based on DQM <3.0>
Transaction DQM<3:0> MA<1:0>
Word 0b0000 0b00
Byte 0 0b1110 0b00
Byte 1 0b1101 0b01
Byte 2 0b1011 0b10
Byte 3 0b0111 0b11
Lower half
word
0b1100 0b00
Upper half
word
0b0011 0b10
Table 6-11. 16-Bit Byte Address Bit MA <0> for Writes Based on DQM <1.0>
Transaction DQM<1:0> MA<0>
Half word 0b00 0b0
Byte 0 0b10 0b0
Byte 1 0b01 0b1
The MSCx[RTx] fields specify the type of memory:
• Non-burst ROM or flash memory
• SRAM
• VLIO
• Burst-of-four ROM or flash memory