User's Manual

© SENSITECH INC. CONFIDENTIAL – CONTROLLED DOCUMENT Page 29 of 83
A Carrier Corp. Company
PART NUMBER T82002163
REV A
Highest Priority- ”Enter Sleep”
“Set_SLFRSH”
“Clear_E1PIN”
“Refresh”
“New_MRS”
“Read/Write”
Lowest Priority - “Auto_Power_Down”
KnRUN = MDREFR[K1RUN] OR MDREFR[K2RUN]
Auto_Power_Down = MDREFR[APD]
Clear_E1PIN = !(MDREFR[E1PIN])
Set_SLFRSH = MDREFR[SLFRSH]
Enter_Sleep = Sleep/Deep-Sleep/Standby/ Frequency Change Request and no more
transactions to process
Auto_Power_Up = Read/Write is asserted during the power-down state OR New_MRS
OR Refresh OR !(MDREFR[APD])
Synchronous, Static, and Variable-Latency I/O (VLIO)
Interfaces
The static memory and VLIO interfaces have six chip selects (nCS<5:0>) and 26 bits of byte
address (MA<25:0>) for accesses of up to 64 Mbytes of memory in each of six banks. Alternately,
a mode is available to support up to two 128-Mbyte chip selects (nCS<1:0>) with 26 bits of halfword
address (MA<0>, MA<25:1>) and two 64-Mbyte chip selects (nCS<5:4>) with 25 bits of
byte address (MA<25:0>). This programmable option resides in the Static Memory Configuration
register SA1110[SXENX]. Each chip select is individually programmed to select one of the
supported static memory types.
• Non-burst ROM or flash memory (Section 6.4.3.2) is supported on each of
nCS<5:0>
• Burst ROM or flash memory with non-burst writes (Section 6.4.3.2) is
supported on each of nCS<5:0>
• SRAM is supported on each of nCS<5:0>
• Variable-latency I/O is supported on each of nCS<5:0>
• Synchronous flash memory is supported on each of nCS<3:0>
The four synchronous-flash memory partitions (nCS<3:0>) are divided into two partition pairs: the
0/1 pair and the 2/3 pair. Both partitions in a pair must be identical in size and configuration. The
two pairs can be different. For example, the 0/1 pair can be 66-MHz synchronous flash memory on
a 32-bit data bus while the 2/3 pair is 33-MHz synchronous flash memory on a 16-bit data bus.
The VLIO interface differs from SRAM in that it allows the use of the data-ready input signal,
RDY, to insert a variable number of wait states. For all static memory types, each chip select can be
configured individually to a 16-bit or 32-bit wide data bus. The nOE signal is asserted on reads, the
nPWE signal is asserted on writes to VLIO devices, and the nWE signal is asserted on writes to all
other static devices, both synchronous and asynchronous. For SRAM and VLIO, DQM<3:0> are
byte enables for both reads and writes. When the processor comes out of reset, it begins to fetch
and execute instructions at address 0x00, which corresponds to memory selected by nCS<0>,
which is the required location of the boot ROM. The BOOT_SEL pin determines the width of the
boot memory.
Asynchronous Static Operation
The static-memory interface is comprised of six chip selects, nCS<5:0>. These six chip selects are