User's Manual

Page 28 of 83

A Carrier Corp. Company

PART NUMBER T82002163

REV A

SDRAM Power-ON State Machine (figure below):

Sleep, deep-sleep, standby, or frequency-change requests cause the SDRAM state machine to enter

the self-refresh and clock-stop state. Software must then complete the appropriate reset procedure. Clearing

MDREFR[E1PIN] and MDREFR[KnRUN] provides software control of the SDRAM memory system low-

power modes.

Note: (1) Use these modes with extreme caution, because the resulting states prohibit automatic toggles

from mode register set, read, write, and refresh commands.

The Auto_Power_Down and Auto_Power_Up transitions (made possible by setting the APD bit in

MDREFR) provide a completely automatic alternative for minimizing power consumption in the

SDRAM system.

(2) Some companion chips require the clock to be present at all times.

Use the following prioritization scheme for transitions out of the NOP state. If enabled with the

APD bit, the Auto_Power_Down transition occurs when none of the higher priority transitions are

asserted. The Auto_Power_Up transitions occur when refresh, New_MRS, or read/write is asserted

during the Power_Down state.