User's Manual

Page 27 of 83

A Carrier Corp. Company

PART NUMBER T82002163

REV A

Programmable SDRAM Memory Map Options (Figure below):

SDRAM State Machine

Figure 6-4 shows the SDRAM controller states and transitions associated with powering on the

PXA27x processor and the SDRAMs properly. Transitions are determined by the overall memory

controller state and a few SDRAM power-down, self-refresh status, and control bits. The states that

involve multiple SDRAM devices are self-refresh and clock-stop, self-refresh, SLFRSH,

PWRDNX, power-down, power-down and clock-stop, PWRDN, PALL, and MRS. The states that

involve single SDRAM partitions are ACT, PRE, READ, and WRITE. The MRS command is sent

once to configure partition pair 0/1 and a separate MRS command is sent only once to configure

partition pair 2/3. The auto-refresh command is issued to memory in the same partition pair at the

same time. Therefore, the chip-select signals representing the partition pair are asserted at the same

time when the MRS command and auto-refresh is issued from the memory controller to a specific

partition pair.