User's Manual

Page 26 of 83

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PART NUMBER T82002163

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Synchronous Dynamic Memory (SDRAM) Interface

The processor supports the JEDEC synchronous dynamic memory (SDRAM) interface. The

SDRAM interface supports four 16-bit or 32-bit wide partitions of SDRAM. Each partition is

allocated 64 or 256 Mbytes of the internal memory map. The actual size of each partition depends

on the SDRAM configuration used. The four partitions are divided into two partition pairs: the 0/1

pair and the 2/3 pair. Both partitions in a pair must be identical in size and configuration. Pairs 0/1

and 2/3 can be different. For example, the 0/1 pair can be 100-MHz SDRAM on a 32-bit data bus,

while the 2/3 pair can be 50-MHz SDRAM on a 16-bit data bus.

The SDRAM interface includes the following:

• Four partition selects, nSDCS<3:0>

• Four byte mask signals, DQM<3:0>

• 15 multiplexed bank/row/column address signals, MA<24:10>, MA<24:23,14:2>, or

MA<24:23,13:1>, depending on the MDCNFG[STACKx] setting

• One write enable, nWE

• One column-address strobe (nSDCAS)

• One row-address strobe (nSDRAS)

• One clock enable (SDCKE)

• Two clocks (SDCLK<2:1>)

The processor performs auto-refresh (CBR) during normal operation and supports self-refreshing

SDRAM during sleep, deep-sleep, standby, and frequency-change modes. An SDRAM autopower-

down mode bit (MDREFR[APD]) can be set so that the two clocks (SDCLK<2:1>) and the

clock-enable signal (SDCKE) to SDRAM are automatically de-asserted whenever none of the

corresponding partitions is being accessed.

Each possible SDRAM section of the memory map is referred to as a partition, to distinguish them

from banks internal to SDRAM devices.

Maximum Row Active Time (TRAS)

The maximum amount of time that any SDRAM row can be active is defined as TRASMAX. When

programming MDREFR[DRI], ensure that the refresh cycle time is less than TRASMAX because it is

not monitored by the memory controller.

Programmable Larger SDRAM Memory Space

The read/write MDCNFG register contains control bits for configuring the SDRAM for larger

SDRAM configurations than fit in the 64-Mbyte SDRAM partitions. Refer to Table 6-23 for

configuration programming. Figure 6-2 shows the programmable option for the SDRAM memory

space.