User's Manual

© SENSITECH INC. CONFIDENTIAL – CONTROLLED DOCUMENT Page 25 of 83
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PART NUMBER T82002163
REV A
SDCLK<0> and does not have any control bits of its own to turn it on or off. Use the buffer
strength field associated with SDCLK<3> to turn off SDCLK<3> if there is no stacked flash in the
system. This buffer strength setting is located in the BSCNTR2 register.
Static partitions 0 and 1 may contain stacked flash. The memory controller must be aware of which
static memory partitions contain stacked flash. This is programmed in the SA1111[SXSTACK]
field. When a flash device is being written to, the nCS and nWE signals swap functionality from a normal
flash write to an off-chip
device. This is shown by timing diagrams in the Intel® PXA27x Processor Family EMTS.
Figure 6-1. General Memory Interface Configuration