User's Manual

Page 24 of 83

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PART NUMBER T82002163

REV A

frequency-change modes

• Provides signals and controls for fly-by DMA transfers

• Supports non-volatile memory configured as bank 0 from either 16- or 32-bit devices

• Provides three independent output clocks (SDCLK<2:0>) that can be turned on/off separately

and can be programmed to be free-running. The clocks can be the same frequency or half the

frequency of the input clock, CLK_MEM. One clock (SDCLK<0>) can also be programmed

as one quarter of the input-clock frequency. A fourth output clock (SDCLK<3>) depends on

configuration bits used to control SDCLK<0>.

• Provides a programmable power-down mode for saving power

Memory Controller Operation

The processor has three different memory spaces: SDRAM, static memory, and PC Card space.

SDRAM has four partitions, static memory has six partitions, and PC Card space has two partitions

(or sockets). When user software performs a memory burst across the boundary between any two

adjacent partitions, the configurations for each partition must be identical. They must have the

same external bus width, burst length, and so forth.

In theory, the partitions can be different types of memory sharing the same configuration

characteristics. In practice, cross-partition memory bursts are conducted only when the two

partitions hold the same memory type. A typical case is a transfer across two SDRAM partitions, 0

and 1, which are mandated to have the same characteristics.

Figure 6-1 is a block diagram of the maximum configuration of the memory controller.

Stacked SDRAM and Flash Memory

This section describes memory types that may be supported in the PXA271 and PXA272

processors.

Stacked SDRAM

On the Intel® PXA271 processor, SDRAM is stacked and connected to SDRAM partition 0. On

systems using the Intel® PXA271 processor, external SDRAM memory chips must not exist within

the same SDRAM partition pair as that of the internal stacked SDRAM. This could cause negative

signal reflection to the stacked SDRAM device.

For the Intel® PXA271 processor stacked SDRAM, the Intel® PXA27x processor memory

controller must be programmed to multiplex the SDRAM address lines out differently because the

address lines to the stacked SDRAM are not connected to the usual MA<24:10> lines. The

MDCNFG[STACKx] field on a Intel® PXA271 processor must be programmed to 0b01 to send the

SDRAM address out on MA<24:23,13:1> for stacked 16-bit SDRAM of this product.

For a non stacked part (Intel® PXA270 processor) or flash only stacked part (Intel® PXA272

processor) the MDCNFG[STACKx] field must be programmed to 0b00 to send the SDRAM

address out on MA<24:10>.

Stacked Flash Memory

A fourth SDCLK, SDCLK<3> is driven by the memory controller, to be used in the PXA271 and

PXA272 processors containing stacked flash devices. SDCLK<3> is a buffer duplicate of