User's Manual
© SENSITECH INC. CONFIDENTIAL – CONTROLLED DOCUMENT
Page 23 of 83
A Carrier Corp. Company
PART NUMBER T82002163
REV A
2) External Power adapter loading evaluation
Charging at 3A only
Charging3A+Loading1.
45v&0.5A
Charging3A+Loading1.
45v&0.5A+3.3V&0.5A
Charging3A+Loading3.3V
&1A+7.2V&3.0A
Charging3A+Loading3.3
V&1A+7.2V&3.3A
AC/DC Adapter
Outpout Voltage(V)
14.9 14.770 14.89 14.71 14.58
AC/DC ADAPTER
OUTPUT CURRENT
(A)
2.32 2.390 2.56 4.58 4.74
PD(W)
34.568 35.300 38.1184 67.3718 69.1092
Note:The adapter 's max PD is 70W.
LogicPD Card Engine
Memory Controller Reset and Initialization
The SDRAM interface is disabled on reset. Reset values for the boot ROM are determined by BOOT_SEL.
BOOT ROM is immediately available for reading upon exit from reset, and all memory interface control
registers are available for writing.
Memory Controller
The internal and external memory-interface structures for the PXA27x processor will be described in detail
below. Memory-related registers that configure the memory controller for data transfers to and from static
and dynamic memory devices are also described.
The external memory-bus interface for the PXA27x processor supports SDRAM, synchronous, and
asynchronous burst-mode and page-mode flash memory, page-mode ROM, SRAM, variable latency
I/O (VLIO) memory, PC Card, and CompactFlash expansion memory. Memory types are
programmable through the memory-interface configuration registers (see Table 6-44).
Memory requests are placed in a four-deep processing queue and processed in the order they are
received.
Features
The memory controller provides the following features:
• Interfaces to internal synchronous flash and SDRAM devices
• Interfaces to four partitions of SDRAM
• Interfaces to up to 1.0 Gbytes of SDRAM
• Supports 1.8-V JEDEC LP-SDRAM operation at 104 MHz
• Interfaces to six partitions of static memory. Four of these six partitions can be synchronous
flash memory.
• Interfaces to up to 384 Mbytes of flash memory
• Interfaces to two sockets of PC Card memory
• Allows an alternate bus master to take control of the bus
• Places the SDRAMs into self-refresh mode before entering sleep, standby, deep-sleep, and