TripStrip II Hardware Specification Document Sensitech Inc. 800 Cummings Center • Suite 258X Beverly, MA 01915-6197 © SENSITECH INC. A Carrier Corp.
Federal Communications Commission (FCC) Statement You are cautioned that changes or modifications not expressly approved by the part responsible for compliance could void the user’s authority to operate the equipment FCC-Class B This equipment has been tested and found to comply with the limits for a class B digital device, pursuant to part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a communications.
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APPROVALS Engineering: Name: ______________________________ Date: ____________________________________________ Signature: ____________________________________________ Quality: Name: _ ______________________ Date: Signature: ______________________________________________ Manufacturing: Name: _______________________________ Date: Signature: ______________________________________________ Marketing: Name: _____________________________ Date: Signature: _________________________________________
Document Version Information ........................................................................................ 9 Organization of this Document ......................................................................................... 9 Executive Summary ........................................................................................................... 9 Device General Description ...............................................................................................
Asynchronous Flash Memory Interface................................................................................. 31 Memory Controller.................................................................................................................. 31 Synchronous Flash Memory ................................................................................................... 32 ROM Interface ...................................................................................................................
Operation.................................................................................................................................. 48 Functional Description ............................................................................................................ 49 Interrupts.................................................................................................................................. 49 Memory Stick Insertion and Removal .......................................................
Program Loading.............................................................................................................. 77 4.1 Understanding the Load Command ..................................................................................... 78 YAFFS (Yet Another Flash File System)........................................................................... 79 8.1 YAFFS Overview ................................................................................................................ 79 8.
Document Version Information Document Functional Requirement Specifications Hardware Specifications Firmware Version T85000530, Rev. A T82002163, Rev. A Organization of this Document This document outlines the TripStripII’s specifications in detail. It describes each aspect of the unit’s functionality and how the hardware is configured. Executive Summary The TripStrip II is a handheld thermal printer which is capable of portable or desktop use.
User Interface Power Charge Paper Out Low Batt User presses the Power Button and the unit is powered ON and the Power LED is ON. The Sensitech application program appears momentarily. The user is now able to download any TT4 (2k/16k) or TTmini; except TT4 USB. To download a TT4 unit, the user may place a TT4 on the optical interface and press START. To download a TTmini, the user may connect the TTmini to the RS232 DB9 connector and press START.
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FRS in brief To re-design the current TripStrip TempTale Remote Printer that provides hardcopy printouts of time/temperature data and related information from TempTale monitors. The current version of the product, while suitable in many applications for most customers has several deficiencies that impede further adoption of TempTale monitoring programs. In addition, the product is RoHS compliant.
Device Hardware Structure General Hardware Information Electrical Specification 1.1 SWITCHING POWER SUPPLY Input Voltage: AC 100~240V Frequency:50/60Hz Input Current: 1500mA. Output Voltage: DC 15V Output Current: DC 4000mA 1.2 DC Input: 12-24V * 15VDC Wall Adapter * 12 VDC automobile DC adapter * 24 VDC trailer truck DC adapter 1.2.1 Input current: 2-5A 1.2.2Power Consumption: approximately 15W 1.3. Charging Max Charging Current:3A Charging Voltage: 8.4V +/- 0.1V Charging Time: 3.
2k monitor = 11 seconds to download the data and an additional 49 seconds to print 16k monitor = 1 minute to download and an additional 6 minutes to print © SENSITECH INC. A Carrier Corp.
Power Save Mode “Suspend State” Suspend state is the PXA270 SOM’s hardware power down state, allowing for lower power consumption. The Suspend state is designed to reduce power consumption while the PXA270 is waiting for an event such as a keyboard input. The suspend state is entered using Logic BSP’s by asserting the nSUSPEND signal or through software. The PXA270 processor is put into Standby Mode. All power supplies remain active. System context is retained. Internal clocks are stopped except RTC.
• • • • • • Fully discharged cells are automatically trickle charged at 10% of the programmed current until the cell voltage exceeds 2.5V/cell. Charging terminates if the low-battery condition persists for more than 25% of the total charge time. The LTC4006 includes a thermistor sensor input that suspends charging if an unsafe temperature condition is detected and automatically resumes charging when the battery temperature returns to within safe limits. The LTC4006 charges a 7.4VDC/6A battery pack.
PARTS LIST Location Specification Size Qty Vendor S-8232ABFT-T2 TSSOP-8 1 SEIKO Q1 Description PROTECTION IC N-CH FET FTD2017A TSSOP-8 1 SANYO R1，R2R 3,R4 CHIP RESISTOR 1Kohm (J) 1608 Size 4 R5 CHIP RESISTOR 4.7Mohm (J) R6 CHIP POWER RESISTOR C1,C2,C3 CHIP CAPACITOR U1 R020ohm 0.
• • • • Additional features include a high voltage bias regulator, automatic switch-over to external bias for improved efficiency, thermal shutdown, frequency synchronization, cycle by cycle current limit and adjustable line under-voltage lockout. The device is available in a power enhanced TSSOP-20 package featuring an exposed die attach pad to aid thermal dissipation 7-42VDC input voltage and converts it to 6.25VDC/7A. This voltage output is for the Print Head. 6. LT1940, Dual Monolithic 1.4A, 1.
9. The CAT5113 is a single digitally programmable 10K potentiometer designed as a electronic replacement for mechanical potentiometers. • The CAT5113 contains a 100-tap series resistor array connected between two terminals RH and RL. • An up/down counter and decoder that are controlled by three input pins, determines which tap is connected to the wiper, RW. • The wiper setting, stored in nonvolatile memory, is not lost when the device is powered down and is automatically reinstated when power is returned.
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Li-ION Charging 1.Charging cycle evaluation (Battery is empty before this charge) Chager IC is 4006 and CHG indicator available only Conditions: Fully Discharge the battery before the charging cycle test. The input power supply is 15V and charging current is 3A Remark: The Max. charging time is around 3 hours.
Charging Current Vs time 00:00 00:10 3.5 00:30 01:00 3 01:30 Current (A) 2.5 01:40:00 02:00 2 02:10:00 02:30 1.5 02:40 02:50 1 03:00 0.5 03:10 03:20 0 00:00 01:00 02:00 02:40 03:10 03:32 03:30 03:32 Battery Voltage During charging 00:00 Battery Voltage (V) 9 00:10 00:30 8.5 01:00 8 01:30 7.5 02:00 01:40:00 02:10:00 7 02:30 02:40 6.
2) External Power adapter loading evaluation Charging at 3A only Charging3A+Loading1. Charging3A+Loading1. Charging3A+Loading3.3V Charging3A+Loading3.3 45v&0.5A 45v&0.5A+3.3V&0.5A &1A+7.2V&3.0A V&1A+7.2V&3.3A AC/DC Adapter Outpout Voltage(V) 14.9 14.770 14.89 14.71 14.58 AC/DC ADAPTER OUTPUT CURRENT (A) 2.32 2.390 2.56 4.58 4.74 PD(W) 34.568 35.300 38.1184 67.3718 69.1092 Note:The adapter 's max PD is 70W.
frequency-change modes • Provides signals and controls for fly-by DMA transfers • Supports non-volatile memory configured as bank 0 from either 16- or 32-bit devices • Provides three independent output clocks (SDCLK<2:0>) that can be turned on/off separately and can be programmed to be free-running. The clocks can be the same frequency or half the frequency of the input clock, CLK_MEM. One clock (SDCLK<0>) can also be programmed as one quarter of the input-clock frequency.
SDCLK<0> and does not have any control bits of its own to turn it on or off. Use the buffer strength field associated with SDCLK<3> to turn off SDCLK<3> if there is no stacked flash in the system. This buffer strength setting is located in the BSCNTR2 register. Static partitions 0 and 1 may contain stacked flash. The memory controller must be aware of which static memory partitions contain stacked flash. This is programmed in the SA1111[SXSTACK] field.
Synchronous Dynamic Memory (SDRAM) Interface The processor supports the JEDEC synchronous dynamic memory (SDRAM) interface. The SDRAM interface supports four 16-bit or 32-bit wide partitions of SDRAM. Each partition is allocated 64 or 256 Mbytes of the internal memory map. The actual size of each partition depends on the SDRAM configuration used. The four partitions are divided into two partition pairs: the 0/1 pair and the 2/3 pair. Both partitions in a pair must be identical in size and configuration.
Programmable SDRAM Memory Map Options (Figure below): SDRAM State Machine Figure 6-4 shows the SDRAM controller states and transitions associated with powering on the PXA27x processor and the SDRAMs properly. Transitions are determined by the overall memory controller state and a few SDRAM power-down, self-refresh status, and control bits.
SDRAM Power-ON State Machine (figure below): Sleep, deep-sleep, standby, or frequency-change requests cause the SDRAM state machine to enter the self-refresh and clock-stop state. Software must then complete the appropriate reset procedure. Clearing MDREFR[E1PIN] and MDREFR[KnRUN] provides software control of the SDRAM memory system lowpower modes.
Highest Priority- ”Enter Sleep” “Set_SLFRSH” “Clear_E1PIN” “Refresh” “New_MRS” “Read/Write” Lowest Priority - “Auto_Power_Down” KnRUN = MDREFR[K1RUN] OR MDREFR[K2RUN] Auto_Power_Down = MDREFR[APD] Clear_E1PIN = !(MDREFR[E1PIN]) Set_SLFRSH = MDREFR[SLFRSH] Enter_Sleep = Sleep/Deep-Sleep/Standby/ Frequency Change Request and no more transactions to process Auto_Power_Up = Read/Write is asserted during the power-down state OR New_MRS OR Refresh OR !(MDREFR[APD]) Synchronous, Static, and Variable-Latency I/O (
configurable for the following: • Non-burst ROM or flash memory • Burst ROM or flash memory • SRAM • VLIO devices The VLIO interface differs from SRAM in that it allows the use of a data-ready input signal, RDY, to insert a variable number of memory-cycle wait states. The data bus width for each chip-select region can be programmed to be 16- or 32-bit. The nCS<3:0> signals are also configurable for synchronous static memory.
• Burst-of-eight ROM or flash memory The MSCx[RBWx] fields specify the bus width for the memory space selected by nCS<5:0>. If a 16-bit bus width is specified, transactions occur across data pins MD<15:0>. Use the BOOT_SEL pin or SXCNFG register to configure nCS<3:0> for synchronous static memory. Asynchronous Flash Memory Interface The MSCx[RDFx] bit fields define the latency for each read access of non-burst flash memory or the first read access of burst flash memory.
Synchronous Flash Memory This section describes how to interface with synchronous flash memory. Synchronous flashmemory operation resets to asynchronous mode (page mode for reads and asynchronous singleword writes). The only way the system can enter synchronous mode (burst-timing synchronous reads and asynchronous single-word writes) is through the Read Configuration register (RCR). Therefore, at boot time, synchronous flash memory operates the same as asynchronous boot ROM.
MSCx[RDF] defines the latency (in memory clock cycles) for the first and all subsequent data beats from non-burst ROMs and the first data beat from a burst ROM. The value of MSCx[RDN] defines the latency for the burst data beats after the first for burst ROMs. Specifying the MSCx[RRR] value allows a delay on the next access to a different memory space to allow time for the current ROM to three-state the data bus.
For both reads and writes from and to VLIO, clearing DCMDx[INCSRCADDR] and DCMDx[INCTRGADDR] causes the source and target addresses not to be incremented to the VLIO interface, which allows port-type VLIO chips to interface with the processor. The only valid memory types for this DMA mode are VLIO and PC Card/CompactFlash devices. For writes to VLIO, if all byte enables are turned off (masking out the data, DQM = 0b1111), then the write enable is suppressed (nPWE = 1) for this write-beat to VLIO.
FIFO buffers data from the serial link until it is read by the processor. In non-FIFO mode, the transmit and receive FIFOs are bypassed. Each UART includes a programmable baud-rate generator that can divide the input clock by 1 to (216 – 1). This produces a 16X clock that can be used to drive the internal transmit and receive logic. Software can program interrupts to meet its requirements, which minimizes the number of computations required to handle the communications link.
— 1, 1½, or 2 stop-bit generation — Baud-rate generation up to 921 kbps for all UARTs — False start-bit detection • 64-byte transmit FIFO • 64-byte receive FIFO • Complete status-reporting capability • Ability to generate and detect line breaks • Internal diagnostic capabilities that include: — Loopback controls for communications-link fault isolation — Break, parity, and framing-error simulation • Fully prioritized interrupt system controls • Separate DMA requests for transmit and receive data services • S
nDSR Input nDCD Input Data Set Ready—When low, indicates that the modem or data set is ready to establish a communications link with a UART. The nDSR signal is a modem-status input. Its condition can be tested by reading MSR[DSR], which is the complement of nDSR. MSR[DDSR] indicates whether the nDSR input has changed state since MSR was last read. This signal is present only on the FFUART. When MSR[DSR] changes state, an interrupt is generated if the modem-status interrupt is enabled.
The receive-data sample counter frequency is 16 times the value of the bit frequency. The 16X clock is created by the baud-rate generator. Each bit is sampled three times in the middle. Shaded bits in Figure 10-1 are optional and can be programmed by software. Each data frame is between 7 and 12 bits long, depending on the size of the data programmed, whether parity is enabled, and the number of stop bits. A data frame begins by transmitting a start bit that is represented by a high-to-low transition.
register before it goes to the pin. When the UART unit is disabled, the transmitter or receiver finishes the current byte and stops transmitting or receiving more data. Data in the FIFO is not cleared, and transmission resumes when the UART is enabled. USB Client Controller: Overview The UDC supports 24 endpoints (endpoint 0 plus 23 programmable endpoints). The UDC is a USB Revision 1.
Features • USB Revision 1.
Operation The UDC consists of four major components: the peripheral bus interface, endpoint memory, endpoint control, and USB interface. The peripheral bus interface contains the UDC control and status registers for the endpoint configuration data and provides the interface between the PXA27x processor and the USB data. The endpoint memory is a 4-Kbyte SRAM used for USB endpoint data storage.
are 53 sources for this interrupt. Each of the 24 endpoints (0 and A–X) has two interrupts: packet complete and FIFO error. In addition, the UDC has five interrupts that can be generated based on USB activity. The interrupt sources are shown in the UDC Interrupt Status registers, which must be read to determine the cause of the interrupt being generated. In addition, USB activity can be determined by reading the UDC Interrupt Status registers.
endpoint, the FIFO Service (FS) and Packet Complete (PC) bits in the Endpoint Control/Status register are set when a complete data packet has been received from the USB host controller. The Byte Count register of each endpoint indicates the number of data bytes that need to be unloaded from the buffer. As data is read from the FIFO memory using the Data register, the corresponding Byte Count register value is decremented to indicate the number of bytes remaining in the buffer.
remote wake-up feature of the UDC, after the UDC has entered the suspend state, sending a wakeup signal to the USB host controller is performed by setting UDCCR[UDR]. Doing so forces the UDC to drive a non-idle state (K state) onto the USB for 3 milliseconds without further user intervention. The UDC hardware then clears UDCCR[UDR].
discussed in detail. Note: The processor does not provide direct connection to or control of the USB Vbus. Figure 12-15. USB OTG Configurations On-Chip OTG Transceiver Operation The USB host port 2 transceiver is designed in accordance with the Pull-up/Pull-down Resistors Engineering Change Notice to the USB 2.0 Specification to provide on-chip resistors and OTGcompliant transceiver operation.
Figure 12-16. Host Port 2 OTG Transceiver Interface to External OTG Transceiver In the case where the user does not use the internal OTG transceiver, the UDC contains control, status, and interrupt registers to provide seamless interfacing to external transceivers. External transceivers can be used to provide D+, D–, and Vbus driver to the USB.
Note: For Figure 12-17, UP2OCR[SEOS] = 4 for USB client and UP2OCR[SEOS] = 5 for USB host. Interface to External Charge Pump Device In addition to the interface options described in Section 12.5.4, the UDC provides control outputs and interrupt inputs to drive and monitor an external charge pump device. To do so, the USB D+ and D– signals can be output using the on-chip OTG transceiver and the Vbus interface provided by an external charge pump device.
Memory Stick Overview The Memory Stick is a medium for storing and transferring data. In its simplest form, the Memory Stick is a small, pluggable card containing flash (or other similar) memory. This memory can store multiple content types—for example, audio data or stored image data. In addition to this basic form, other devices are available that use the standard Memory Stick definition (for example, camera modules).
Functional Description The Memory Stick system, depicted in Figure 17-1, consists of the memory stick host controller and an attached Memory Stick card. Figure 17-1. Memory Stick System Block Diagram The memory stick host controller interfaces with the Memory Stick using a 32-bit internal application interface. It allows: • Sending of transfer protocol commands (TPCs) to the Memory Stick using the MSHC Command register.
Software must monitor the nMSINS interrupt. When an interrupt occurs due to the removal of the memory stick, the software must halt all MHSC activity and reset the memory stick host controller. Reset The memory stick host controller is reset in either of two ways: • Any PXA27x processor reset causes all of the MSHC registers to be reset. • Setting MSCRSR[RST] causes the memory stick host controller to enter and remain in reset until MSCRSR[RST] is cleared.
LogicPD Card Engine: © SENSITECH INC. A Carrier Corp.
© SENSITECH INC. A Carrier Corp.
© SENSITECH INC. A Carrier Corp.
Note: Our current Card Engine does support Ethernet. Card Engine: © SENSITECH INC. A Carrier Corp.
TempTale Mini During normal monitor operation, communications mode is disabled. In order to enable the communications mode by means of the communications enable pin on the RS232 connector located inside the monitor. This pin must be held during the entire communications session. The monitor communicates via a standard RS232, 9600 baud rate, 8 bit, No Parity, 2 Stop bit protocol.
timer. This timer is used as a count down timer that determines the timeout period for communications between the monitor and host PC. Effectively what this means is that as long as this timer is refreshed and not allowed to expire, communications mode will stay active allowing commands to be sent. The monitor refreshes this timer any time valid command is sent, so as long as commands continue to be sent, the monitor will continue to refresh the timer.
Figure 1 HOST PC ULCM PACKET COMMAND PROTOCOL MONITOR Command Echo back command 0x00 or Parameter Packet Executes Command Status Data Packet Note: All data packets will consist of a 3 byte checksum position followed by the requested data ending with a Checksum The command parameter packet and data packet use the same packet format, which is shown below: Packet Data 3 byte count of the number of parameters or data bytes to follow B0 B1 B2 Checksum Parameter or Data bytes D0, D1, D2, D3, ……….
If the packet contains 1120 data bytes and the value of all the bytes is a hex 76 then the sum of the count bytes and data bytes is as follows: Count Byte 0 Count Byte 1 Count Byte 2 0x60 0x04 0x00 460 H (112 0D) Data Byte 0 Data Byte 1 Data Byte 2 . . . Data Byte 1119 Data Byte 1120 0x76 0x76 0x76 . . . 0x76 0x76 D at a Sum equals 0x208A0 P a c k e t D a t a Sum Once the sum has been calculated, only the least significant byte, in this case 0xA0, is used as the checksum. © SENSITECH INC.
TempTale 4 (Epson TT4) Deleted: RS232 Command Transmission Paradigm As a method of ensuring data integrity, the unit will always echo commands back to the host computer as it receives them. In this way the external device will know that the unit received a specific command correctly. This method allows the host computer to respond in the fastest way.
CMD_UNKNOWN 0x02 BAD_PASSWORD 0x03 BAD_TEMP 0x04 IIC_TIMEOUT 0x05 BAD_INIT 0x07 UNIT_NEW UNIT_SLEEPING UNIT_SDELAY UNIT_RUNNING UNIT_STOPPED 0x0A 0x0B 0x0C 0x0D 0x0E The requested command is not part of the unit's API. This is returned when a command does not exist. This error code is also returned if a command that is sent requires a higher access level than the user is presently in. During the course of logging into the unit, the supplied password is incorrect.
to deal with erroneous communication attempts. Movement from layer 0 to layer 1 is designed to eliminate these issues. Communication is initiated by transmitting a startup sequence of bytes to the unit. This sequence is designed to give the unit time to wake-up, respond, and synchronize to the host computer’s baud rate. Unless all steps are performed correctly, the unit will assume bad communications and return to what it was doing. The bytes transmitted are as follows.
TempTale 4 (OKI TT4) Communications The Monitor has an Infrared optical interface as its primary means for communication to the outside world. There are also provisions made on the PCB for a hard-wired asynchronous 0 to +3 volt logic level output. On the optical port, an infrared phototransistor is used to sense data being input to the device and an infrared LED is used to transmit data out of the device.
Establishing a Connection During normal monitor operation, communications mode is disabled. There are two ways to enable the monitor’s communications mode. The first method is for an external device to trigger the monitor’s internal reed switch by means of a magnet. If this approach is used, the magnet must keep the reed switch triggered during the entire communications session.
Step # Host PC’s Action Monitor’s Action Action Description 1 Send 00h Wake-up Monitor by sending 1 byte 2 Rcv Protocol ID and set-up for correct protocol Send 55h Rcv 00h byte or timeout and start over Send 4 byte login value Rcv 00h and discard Send Protocol ID, low byte 01h, high byte 00h Rcv value and verify it is a 55h Send 00h byte or terminate login process Rcv 4 byte login value and verify Rcv 00h byte or timeout and start over Send 00h byte or terminate login process 3 4 5 6 Acknowle
In the case above where the host computer correctly receives a 0h back from the monitor, the host will then send the final 4-byte login sequence to the monitor. The final sequence of 4 bytes is 7Ah, 5Eh, 8Ah, and A1h. The monitor should receive the 4 values from the host computer and verify whether or not they are correct. If it determines the values were received correctly, it will send back a 1-byte value of 0h.
communications. The figure below illustrates a typical Omega TT4 Standard Command exchange between the host and monitor: HOST PC TT4 PLUS STANDARD COMMAND PROTOCOL MONITOR Command Echo back command 0x00 or parameters Executes Command Status Any additional data As can be seen in the diagram, the host initiates a command by sending a command value to the monitor. The monitor then echoes back the same command value.
indicates an error. A list of valid status codes with their names and descriptions are in the table below: Status name CMD_SUCCESSFUL CMD_UNKNOWN Code 0x00 0x02 BAD_INIT 0x07 Description Returned upon successful completion of command. The requested command is not part of the unit's API. This is returned when a command does not exist. The unit cannot be initialized due to erroneous information having been stored in its configuration pages.
The command parameter packet and data packet use the same packet format, which is shown below: Packet Packet Data 3 byte count of the number of parameters or data bytes to follow B0 B1 B2 Checksum Parameter or Data bytes D0, D1, D2, D3, ……….
TT4 Optical Interface Circuit The circuit consists of a NAND gate IC which inverts the TX signal (input). The input UP_UARTC_TX (B) is High and the input (A) is High, then the output is Low and the LED will not conduct. However, when the TX line transitions from a High to Low state, then the NAND gate output is High which the LED will begin to conduct. The UP_UARTC_RX line is Low when light turns the Phototransistor ON.
Interface Signals: Pin No. 1 2 3 4 Symbol VDD VSS VLCD FLM 5 6 7 8 9 10 11 N/C CL1 CL2 D0 D1 D2 D3 12 /DISPOFF 13 14 VLED VLSS Function POWER SUPPLY FOR LOGIC CIRCUIT GROUND POWER SUPPLY FOR LCD DRIVING VOLTAGE THE FLM SIGNAL INDICATING THE BEGINNING OF EACH DISPLAY CYCLE N/C DISPLAY DATA LATCH DISPLAY DATA SHIFT DISPLAY DATA DISPLAY DATA DISPLAY DATA DISPLAY DATA CONTROL LCD ON/OFF “L”: DISPLAY OFF, “H” DISPLAY ON POWER SUPPLY FOR LED B.L POWER SUPPLY FOR LED B.
BUTTONS FUNCTIONS 1. Navigate to previous window or selection. Cancel. 2. Execute command/entry. Executes menu structure. 3. Navigate up 4. Navigate down 5. Navigate left 6. Navigate right 7. Download TT4 or TTmini and Print data 8. Initiate power to the unit or power OFF 1. BACK 2. ENTER 3. UP Arrow 4. DOWN Arrow 5. LEFT Arrow 6. RIGHT Arrow 7. START 8. POWER Keypad The keypad will consist of 8 buttons which will provide control of the following functions.
9.0 Battery Low Alert Function: The Trip Strip II has a LED indicator which will indicate a low battery condition by steady red LED. The circuit is comprised of two Comparators. If the Vin(+) terminal is Low and the Vin(-) terminal is High, then the output is Low (current will flow). However if the Vin(+) terminal is High and the Vin(-) terminal is Low, then the output is High (current will not flow). Therefore, If the Load in the variable input (5 – 27VDC) is <= 6.5VDC, then the Low Batt LED will be ON.
Motor driving pulse rate: Motor driving speed varies with driving voltage. It is determined with the following formula: Motor driving speed (pps) = [200 * (Vp) – 600] Therefore, for our application Vp = 6.25VDC. As a result, [200 * (6.25) – 600] = 650 pps 11.0 Control Board Dip Switch Setting: Pin No. DS1-1 1-2 1-3 1-4 1-5 1-6 1-7 1-8 © SENSITECH INC. A Carrier Corp.
Note: 1-5 to 1-8 configurations (above) indicate 19,200 bps Baud Rate. When BUSY signal is “LOW”, data from the host can be received. During a “HIGH” state, data cannot be received. This control board incorporates a 2K byte buffer. Therefore, large amount of data can be buffered in input buffer and the Host side can be released immediately. © SENSITECH INC. A Carrier Corp.
Printer Control Board Pinouts: © SENSITECH INC. A Carrier Corp.
Device System Configuration Information LogicLoader (LoLoTM) LogicLoader Overview The LogicLoader (LoLo) is a bootloader/firmware-monitor program developed by Logic Product Development. LogicLoader is designed to initialize an embedded device, load and bootstrap an operating system, and provide a low-level firmware monitor with debugging functionality. LogicLoader Basics Most operating systems rely on an underlying bootloader to initialize a device from its reset condition.
needs. LogicLoader can also be augmented with functional test software to completely verify a device before it leaves the manufacturing line. Here is an example scenario: LogicLoader could launch a device’s final functional test at the end of a manufacturing line, and then load the device’s final software image before packaging. Contact Logic for more information on using LogicLoader to streamline manufacturing.
4.1 Understanding the Load Command The purpose of the ‘load’ command is to transfer an executable image to a device. The image must be in one of the following supported formats: ELF, SREC, RAW, or BIN. The ‘load’ command uses information inherent to the supported formats (or as entered as part of the command for RAW format) to determine where in the device’s memory the downloaded image should be stored. The image must be destined to run from either flash memory, system RAM, or on-chip SRAM.
YAFFS (Yet Another Flash File System) 8.1 YAFFS Overview The acronym YAFFS stands for the phrase "Yet Another Flash Filing System." YAFFS was developed by a company named Aleph One Limited and incorporated by Logic Product Development into the LogicLoader (LoLo) software program. Logic selected YAFFS to fill its file system requirements due to the flexible nature of the program, its licensing scheme, and the fact that it is available for Linux, Windows CE, and other operating systems.
8.2.2 Formatting YAFFS Partitions All file systems need to be formatted before they can be mounted. Because YAFFS was designed from the ground up to work with embedded flash technologies, it understands an 'erased' flash device to be both formatted and empty. To prepare your partition for mounting, simply use LogicLoader's 'erase' command to erase the area of flash where the partition is to be located.
losh> mount yaffs /data Of note is that the 'drive addr' argument is not used when mounting a YAFFS partition. Also of note is that the 'point' argument needs to correspond to the name of the partition (as defined by the add-yaffs command) preceded by a forward slash. LogicLoader needs to mount all YAFFS partitions at the rootdirectory level. Thus, a partition added using: 'add-yaffs boot ...' will be mounted using: 'mount ... /boot'.
Explanation of Script losh> erase B10 B256 /dev/nand0 Purpose of erase command: This command erases non-volatile . When using a memory mapped device (such as NOR flash) the and parameters indicate the memory address and the length in bytes. When using a block device (such as NAND flash) the and indicate the first block number and the number of blocks to erase.
losh> mount fatfs /cfs Purpose of mount command: This command mounts a filesytem of type onto LoLo's root filesystem at point . If the mount command is successful, you may use other shell commands to access the new filesystem. losh> cp /cf/NK.BIN /boot/NK.BIN Purpose of cp command: This command is used to copy a file. losh> config CREATE Purpose of Config command: This command saves and/or displays configuration information in the config device.
