Technical data

Appendix
27.2 Memory Areas of S7 CPUs
Programming with STEP 7
574 Manual, 05/2010, A5E02789666-01
27.2.3 System Memory
27.2.3.1 Using the System Memory Areas
The system memory of the S7 CPUs is divided into address areas (see table below). Using
instructions in your program, you address the data directly in the corresponding address area.
Address Area Access via Units of
Following Size
S7 Notation
(IEC)
Description
Input (bit) I At the beginning of the scan cycle, the
CPU reads the inputs from the input
modules and records the values in this
area.
Input byte IB
Input word IW
Process image input
table
Input double word ID
Output (bit) Q During the scan cycle, the program
calculates output values and places
them in this area. At the end of the scan
cycle, the CPU sends the calculated
output values to the output modules.
Output byte QB
Output word QW
Process image output
table
Output double word QD
Memory (bit) M This area provides storage for interim
results calculated in the program.
Memory byte MB
Memory word MW
Bit memory
Memory double word MD
Timers Timer (T) T This area provides storage for timers.
Counters Counter (C) C This area provides storage for counters.