User's Manual

Model 1150A DVOR
2-26 Rev. - November, 2008
This document contains proprietary information and such information may not be disclosed
to others for any purposes without written permission from SELEX Sistemi Integrati Inc.
Refer to page 2 of Figure 11-21. Circuit U22 is a phase comparator circuit that forms part of the phase control loop
of the Sideband Generator. The reference phase (SB1_REF_PHASE) is the unmodulated CW signal that is sampled
after the manual phaser. The SB1_RF_SAMPLE1 signal is a sample of the final output signal from the from the
forward power coupler DC1. The phase detector is most accurate when the Input A (INPA) and Input B (INPB)
ports are separated by 90 degrees. The output at VPHS is 0.9 Vdc when the phase difference is 90 degrees. The
voltage is 0 volts at 0 degrees and 1.8 volts at 180 degrees. Circuit U20A buffers the detected phase signal. A
sample of the U22 voltage reference of 1.8 VDC is applied to resistors RN1E and RN1G which divide this to 0.9
Vdc. Circuit U20 inverts the detected phase. Analog multiplexer U18 is not active in DVOR mode. In CVOR mode
the SB1_BI_PHASE_CVOR signal is used to switch between the inverted and non-inverted detected phase signals
to remove the bi-phase modulation created by U6.
The output of U18 is applied to the phase error amplifier U14A. The non-inverting input of U14A is connected to
the 0.9 Vdc created from the U22 voltage reference. Error amp U14A drives the output at pin 1 so that the input at
pin 2 equals 0.9 V. The multiplexer U16 is normally open from pin 1 to the S1 output. The switch closes making the
error amplifier a unity gain buffer when the phase loop is unlocked in order for the voltage to move through the
entire range to find the correct lock voltage.
Operational amplifier U14Bprovides a gain of 2 and adds a DC offset from R1. This sets the normal operating
voltage of the phasers in the control loop. This set point will be different for each operating frequency and must be
adjusted during alignment. The output (SB1_MEAN_DYN_PHASE) is routed to each of the phase shifters.
Comparators U12A and U59A compare the error voltage from the U14A output to a fixed voltage of 3.4 V. If the
error voltage is between 0.8 Vdc and 3.4 VDC then the loop is locked and the U12A and U59A outputs are high. If
the voltage falls outside 3.4 and 0.8 Vdc then the output is low and C109 is discharged. R88 then charges the voltage
back high in order to stretched the unlock time. Comparator U12B output goes low when the loop is not locked and
causes U16 to close.
Refer to page 6 of Figure 11-21. The 48 VDC enters the Sideband Generator and enter fuses F1 and F2. Fuse F1
feeds DC to DC converter PS2. The output of PS2 is 24 VDC that primarily supplies the operating voltage for the
final transistors Q4 and Q6 through L91.
The +48 Vdc signal is applied to fuse F2 and then applied to the switching voltage regulator U42. Regulator U42
provides a rectangular pulse train at the VOUT pin. Indictor L85 and C273 filters the pulse train into a DC voltage.
A sample of the DC voltage is applied to the FB (feedback) pin of U42 which allows correction of the pulse train
pulse width to provide +5 VDC at the output. Diode CR32 along with R231, C269 and Q8 provide over voltage
protection. If the voltage exceeds 5.6 volts then Q8 is turned on which will blow the fuse F2.
Linear regulator circuit U44 provides regulation of the +5 Vdc to +3.3 Vdc. DC-DC Converter PS1 converts the 5
Vdc to +15 VDc and -15 Vdc. Linear regulator U45 converts the -15 Vdc to -12 Vdc. Linear regulator U46 converts
the +15 Vdc to +12 Vdc.
Refer to sheet 6 of Figure 11-21. Resistors R249, R250 and diode CR44 provide a precise +10Vdc source for the
voltage monitor circuits. Voltage comparators U49A and U49B monitor the 5 Vdc supply and if the voltage exceeds
the range 4.5 to 5.5 Vdc then one of the comparator outputs will go low turning off both Q11 and Q12. Voltage
comparators U49C and U49D monitor the 12 Vdc supply and if the voltage exceeds the range 10.8 to 13.2 Vdc then
one of the comparator outputs will go low turning off both Q11 and Q12. Voltage comparators U50A and U50B
monitor the 24 Vdc supply and if the voltage exceeds the range 22.3 to 26.3 Vdc then one of the comparator outputs
will go low turning off both Q11 and Q12. Voltage comparators U50C and U50D monitor the -12 Vdc supply and if
the voltage exceeds the range -10.9 to -13.1 Vdc then one of the comparator outputs will go low turning off both
Q11 and Q12. FET Q11 provides an output to the Facilities CCA that is low when the power is ok and high when
the power is out of tolerance. FET Q12 control the front panel power OK LED. When power is normal the gate of
Q12 is high and the drain is low turning the LED CR45 on. The lamp test input (~TEST) goes low when the switch
on the LCU is depressed and causes the LED CR45 to go on.