User's Manual

Model 1150A DVOR
Rev. - November, 2008
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to others for any purposes without written permission from SELEX Sistemi Integrati Inc.
2-25
The signal then enters the Bi-phase modulator circuit. This circuit provides either 0 or 180 degrees of RF phase shift.
I
n a DVOR the selection is controlled by jumper J11 (SB1_BI_PHASE_CVOR is low) to allow operation over the
band from 108 to 118 MHz. In a CVOR the SB1_BI_PHASE_CVOR changes from low to high with each
sinusoidal lobe of modulation signal. This technique is used to remove the carrier from the sideband signal (carrier
suppression) necessary for a CVOR sideband signal. Analog multiplexer U4 switches between the S1 and S2 inputs
to alternately provide +12 or -12 Vdc to R23 and the control pin of the U6 modulator.
After the bi-phase modulator the signal passes through a 6 dB attenuator formed by R26, R28, and R30. The signal
then passes through phase shifters formed by T5, T7, and T9 which are controlled by the phase control loop. The
signal is then amplified by U9 with a fixed gain of 20 dB.
The signal then passes through a 6 dB attenuator formed by R55, R56, and R58. The signal then enters the voltage
controlled attenuator circuit. The SB1_PIN_MOD signal controls the voltage that Q2 applies through R73 and the
current through PIN diodes CR22, CR24, CR27 and CR28. The capacitance of the diodes varies with the current
through the diodes and therefore the attenuation changes with current. The other half of diodes CR22, CR24, CR27
and CR28 are biased on continuously to provide a nominal voltage at R60, R70, R74 and R81.
After the PIN diode attenuator the signal enters the U11 amplifier with a fixed gain of 20 dB. The signal
(SB1_DRIVER_RF) passes through a 3 dB attenuator and is amplified by FET Q3. The output level is about 2 watts
peak. The Potentiometer R137 sets the gate bias level. This is normally set for 250mv across R141. The gate bias is
turned off with Q15 and Q16 when the shutdown signal (~TX_SHUT) is low to reduce power dissipation.
After amplification by Q3 the signal passes through a 3 dB attenuator formed by R145, R146, and R147. The signal
is then amplified by the final FET Q4. The gate bias is set with R150 to approximately 50mV across R156. The gate
bias is turned off with Q15 and Q16 when the shutdown signal (~TX_SHUT) is low to reduce power dissipation.
The signal then passes through a low pass filter to remove second and higher harmonics of the carrier. The signal
then passes through directional couplers DC1 and DC2 before exiting the board at P2:E. Directional coupler DC1
provides a sample of the forward power to the phase and amplitude control loops. Directional coupler DC2 provides
a sample of the reflected power to the Phase/Magnitude circuit U33 through a 22 dB attenuator. A sample of the
forward power passes through the 30 dB attenuator and into the Phase/Magnitude circuit U33. The levels are set so
that U33 provides 0.9 VDC at the VMAG output when the return loss is 20 dB. The VMAG output is buffered by
U31B and enters the comparator U30a. The positive input to the comparator is a sample of the reference voltage
from U33 divided by 2. If the negative input to the comparator is above the reference then the output of U30A goes
low triggering the one shot U29B and sets the ~SB1_VWSR_ALARM line low. This line goes out of the CCA to
the Audio Generator CCA and reports the indication on the PMDT.
The modulation signal (SB1_Audio) from the Audio Generator is a sinusoidal signal at 30 Hz for a CVOR or 360
Hz for a DVOR. This signal passes through DC blocking cap C251 and through buffer U38C. The output of buffer
U38C feeds both inverter U38D and the analog multiplexer U25. The SIN_BIPHS signal that originates from the
Audio Generator is high when the SB1_AUDIO signal is positive and low when it is negative. Multiplexer U25
switches between the positive (U38C) and negative (U38D) inputs to generate a rectified sin wave signal.
Multiplexer U26 passes the signal when the SB1_ENABLE line is high. Potentiometer R142 is used to add an offset
to the output of U26 and set in the factory. Operational amplifier U27A provides a gain of 3 with high frequency
attenuation. The signal enters error amplifier U27B which drives the PIN diode modulator circuit. A sample of the
forward power is detected by linear detector U32 and buffered by U31A and applied to the inverting input of the
error amplifier U27B for reducing the modulation harmonics of the sideband output. Amplifier U34 drives the front
panel test point TP2 and the SB1_FWD signal sent to the Audio Generator. Potentiometer R2 is used to calibrate the
output level to match external test equipment value for output power.