User's Manual

Model 1150A DVOR
Rev. - November, 2008
This document contains proprietary information and such information may not be disclosed
to others for any purposes without written permission from SELEX Sistemi Integrati Inc.
2-19
The outputs of DACs U18-6 and U18-8 are input to op-amps U34C-10 and U34D-12 as SB1_MOD and SB3_MOD.
T
he outputs of DACs U20-6 and U20-8 are input to op-amps U34A-3 and U34B-5 as SB2_MOD and SB4_MOD.
The power levels of DACs U44-16, U18-1 / U18-2, and U20-1 / U20-2 are set by DACs U31-6, U32-3, U32-4, U32-
5, and U32-6. DACs U31, U32, and U33 are directly written by DSP U6. DACs U32 establish the sideband
modulation levels while DACs U33 set the sideband phase levels. The DACs U32-2 and U32-1 reference inputs are
programmed by DAC U32-5 while DAC U33-2 and U33-1 reference inputs are programmed by +VREF (mentioned
previously).
The SBOx_LEVEL outputs of DAC U32 are summed into op-amps U34A, U34B, U34C, and U34D and further
conditioned by op-amps U35A, U35B, U35C, and U35D before routing to connector P1-C21, P1-C22, P1-A21, and
P1-A22 as SBx_AUDIO. The corresponding SBOxAM signals are available on test points TP18 through TP21.
The SBxPH outputs of DAC U33 are current-limited by resistors R55 through R59 before routing to connector P1-
A28, P1-A30, P1-A32, and P1-B28 as SBx_PHS. The SBxPH outputs of DAC U33 and the SBOx_LEVEL outputs
of DAC U32 route to multiplexer U54 for monitoring by DSP U6.
PLD U40 internally adds an offset to the CARRAM addresses of 7.5 degrees if header JP3-4 / JP3-3 pins are
connected and ground-check signals GSC0+ (P1-C10) and GSC0- (P1-C11) from the Monitor CCA are translated as
logic high by RS422-TTL converter U38-2. PLD U40 clears its internal audio RAM counters if logic U19 interprets
that this Audio Generator is not on the antenna (U19-4 as ~TX_IND is logic high) and a rising edge of AUD_SYNC
(output of RS422-TTL converter U39-2) is detected on PLD U40-40. The rising edge of AUD_SYNC indicates the
start of a new cycle by the other Audio Generator (which is on the antenna).
The DVOR_B configuration input (a buffered DIP switch from the Control Backplane via connector P1-B16) of
PLD U40-126 determines if the SB1/3 (U40-19) and SB2/4 (U40-18) bi-phase outputs cycle at 720 Hz DVOR or 30
Hz CVOR rates. Both of these outputs are buffered by buffer U25 as SIN_BIPHS and COS_BIPHS before routing
to connector P1-C31 and P1-C29.
Commutator switch controls DVSC0 (U40-10) through DVSC5 (U40-23) are generated by PLD U40 during audio
RAM cycling. They are converted by TTL-RS422 converters U21 and U22 if this Audio Generator is on the antenna
(U19-4 as ~TX_IND is logic low) and transient-voltage protected by TVS CRN1 and CRN2 before routing to
connector P1. DVSC5 (U40-23) is also buffered by U46 and presented as SYNC on front panel test point TP3.
PLD U40 is factory programmed using in-system programming (ISP) header J3.
DSP U6-35 can shut down the transmitter by taking TX_OFF high; turning on transistor Q3 and taking ~TX_SHUT
of buffer U25-17 and connecter P1-A27 low. DSP U6-47 can read transmitter on/off status signal ~TX_SHUTB
from buffer U25-3.
2.3.2.4
CSB Power Amplifier Assembly (1A5A3, 1A5A4)
2.3.2.4.1CSB Power Amplifier Assembly Block Diagram Theory
Refer to Figure 2-9. The Carrier Amplifier amplifies and amplitude modulates the input RF carrier to a level that is
acceptable for a 100 watt output at the top of the VOR transmitter cabinet. The modulation is done with 9960 Hz,
30 Hz, keyed 1020 Hz, and voice as needed. The carrier amplifier assembly is made with a single board layout.
The layout consists of all necessary local power supplies that are converted from a single +48V nominal input. The
amplifier assembly has all necessary shutdown signals to stop transmission in case a fault should occur. The Carrier
Amplifier Assembly takes the low level signal from the synthesizer assembly, amplifies, modulates, and filters it,
then applies it to the output for antenna distribution. The Carrier Amplifier Assembly accomplishes the
amplification and modulation using two LDMOS type RF FETs.