User's Manual

Model 1150A DVOR
2-18 Rev. - November, 2008
This document contains proprietary information and such information may not be disclosed
to others for any purposes without written permission from SELEX Sistemi Integrati Inc.
Oscillator Y1 (available at test point TP22) clocks DSP U6-10 and UART U14-13 at 10 MHz through buffers U5D,
U5E and U5C. Supervisor U13 will reset (~RESET) DSP U6-13 if the +3.3V supply drops too low, if
~EXTERN_RESET is active on SPI header J1-2 (factory only), if ~MRESET is active on connector P1-B16
(filtered by inductor FL1 and capacitor C65), or if watchdog (WDOG) from DSP U6-50 doesn’t transition often
enough.
The ~RESET output (available on test point TP7) also restarts flash RAM U1-10 / U2-10, latch U27-1, DACs U31-
28 / U32-24 / U33-24, and PLD U40-127. Finally the ~RESET output (U13-7) is inverted to RESET (U5F-12) for
initializing UART U12-36 and decoder U26-5.
DSP U6 utilizes external memory which includes 512Kx16 of flash ROM (U1 and U2), 16Mx16 of synchronous
DRAM (U4), and 32Kx8 of non-volatile RAM (U3) as well as some internal cache memory. The internal memory
as well as other parts of DSP U6-25 are powered by +1.2V (available at test point TP26) which is created by charge-
pump transistor Q1, diode CR2, and capacitor C34. DSP U6 status is indicated on the front panel by CPU_OK LED
CR3.
The address and data busses of DSP U6 are buffered by buffers U7-U11 before distribution to the most of the CCA.
Only SDRAM U4 is unbuffered to DSP U6 address and data busses due to its communication rates of up to 100
MHz. Emulator header J2 provides accessibility to DSP U6 for in-factory testing.
Decoder U26 defines address spaces for several components of the CCA. Configuration switches on the Control
Backplane CCA are read by DSP U6 through buffers U29 and U30. Synthesizer and sideband digital I/O is
controlled through latch U27 and SPI / SPORT buffers U28 and U24.
CODEC U51 contains two 16-bit analog-to-digital (ADC) converters and two 16-bit digital-to-analog (DAC)
converters. One ADC / DAC pair processes voice input MIC+ from connector P1-C3 and voice / ident output
through op-amps U52A and U50 (available at front panel test point TP2) and op-amps U52B and U53 as
CARR_MOD+ and CARR_MOD- at connector P1-A12 and P1-B12. The other ADC of CODEC U51 converts over
24 channels of power levels, phase levels, and audio levels switched through multiplexers U54 and U48.
CODEC U51 responds to DSP U6 SPORT0 (U6-72, U6-74, U6-75, U6-69, and U6-68) and Timer2 (U6-77)
controls. The +AVCC power supply of CODEC U51-20 is created by the filtering of +3.3V by inductor L6 and
capacitors C135, C136, C137, and C139.
Channel selection of multiplexers U54 and U48 is controlled by DSP U6 through PLD U40 signals MA0 through
MA5. MA4 (U40-121) is the output enable of multiplexer U54-18 while MA5 (U40-112) is the output enable of
multiplexer U48-18. MA0 (U40-87), MA1 (U40-86), MA2 (U40-111), and MA3 (U40-60) select one of sixteen
channels on each multiplexer but only the enabled multiplexer output is switched to buffer U50A before routing to
CODEC U51. Op-amps U47A and U47B condition the CARR_FWD+/- and CARR_RFL+/- signals before
multiplexer U48-19 and U48-20 while the SBx_FWD and SBx_RFL signals are passively filtered before entering
multiplexer U48.
DSP U6 has direct read / write access to the 32Kx16 of CARRAM U41 / U42 as well as the 32Kx16 of SBRAM
U43 / U45 through PLD U40. The address / data bus and control signals of DSP U6 are piped directly through PLD
U40 to the RAMs when not in cycling mode. When in cycling mode, the RAMs address and control lines are
connected to internal counters of PLD U40. The internal counters of PLD U40 read the contents of every location of
the RAMs in 1/30 of a second; a time division of the 19.6608MHz oscillator Y2 into PLD U40-125.
While the contents of an accessed CARRAM address are on the data bus, PLD U40 activates the ~CARDAC signal;
writing the data into DAC U44. Op-amp U37A-1 gains the DAC U44 outputs to create REF_MOD; which inputs to
op-amp U52B (mentioned previously) and eventually as part of the CARR_MOD+/- signals.
While the contents of an accessed SBRAM address are on the data bus, PLD U40 activates the ~SBDAC and
SBDAC_A1 signals; writing the lower byte of data into DACs of U18 and the upper byte of data into DACs of U20.