User's Manual

Model 1150A DVOR
Rev. - November, 2008
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2-13
HY1 provides a DC output that is proportional to the phase difference between the reference input signal and the
v
ariable input signal. When the two signals are in quadrature (the normal operating condition), the output is zero
volts. Output voltage increases with the variable phase input signal delayed with respect to the reference phase, and
decreases with the variable phase input signal advanced with respect to the reference phase. Resistor R87 provides
the proper terminating impedance for the hybrid phase detector output.
The output of the phase detector hybrid HY1 takes two paths. One is referred to as the “mean phase” correction
path, the other the “dynamic phase” correction path.
The mean phase path is DC coupled, with a very low frequency bandwidth. This path serves to correct for any long-
term phase drift with temperature, etc, within the carrier power amplifier assembly in the VOR system. The phase
error voltage developed by phase detector HY1 is applied to the inverting input of integrator amplifier U15. This
amplifier provides a very high gain to DC signals, with limited gain for AC components.
The output of integrator U15 is low pass filtered further by R65 and C55, then applied to the phase error amplifier
U13:A. The output of U13:A controls the tuning voltage on the varactor diodes contained in the phase shifter
network. This control voltage causes the phase shifter network to provide the proper phase shift to the synthesizer
module carrier output signal to force the output of the phase detector hybrid HY1 to zero volts. This locks the DC
component of the system carrier power amplifier output phase to the reference phase within the synthesizer module.
When the VOR system carrier power amplifier amplitude modulates the carrier output signal, it also causes
inadvertent phase modulation. In the DVOR system, this appears as a 30Hz phase modulation, with components at
harmonics of 30 Hz. This is referred to as the dynamic phase shift.
The output of phase detector HY1 is AC coupled through capacitor C59 and phase lead network C61/R71 to the
non-inverting input of phase error amplifier U13:A. The high pass frequency response of this network is chosen to
provide adequate gain to the 30 Hz and above components of the phase error signal, but minimal low frequency
(down to DC) gain to avoid interaction with the mean phase signal processing described above.
This AC coupled path is referred to as the dynamic phase correction path. The dynamic phase error signal is
amplified by U13:A, applied to the phase shift network, and provides a “counter modulation” effect to minimize the
phase distortion in the VOR system carrier output signal.
Carrier frequency RF signal from the Carrier PLL Synthesizer is applied via J2 to the input of the carrier phase shift
network, or phaser.
For additional details on the carrier phase shift network (phaser), refer to sheet 2 of the 012263 schematic diagram,
Figure 11-11. RF from the carrier synthesizer loop is applied to pin 3 of transformer T1. Transformer T1 along
with capacitors C62 and C65 function as a 4 port hybrid, or 90 degree power splitter. RF energy applied to pin 3 is
split equally into two parts at pins 1 and 2, with 90 degrees of phase difference between pin 1 and pin 2. Pins 1 and
2 are terminated with series LC circuits consisting of L9/CR3 at pin 1, L11/CR4 at pin 2. Inductors L10 and L12 are
RF chokes, providing high RF impedance with DC connections to ground for varactor diode control voltage
reference. The capacitance of the varactor diodes is changed by varying the control voltage applied to the cathodes,
with a RF ground provided by C64. With the purely reactive load presented to pins 1 and 2 by the two series LC
networks (L9/CR3 and L11/CR4), the RF energy is reflected back into pins 1 and 2, with the phase of the reflected
signal changed by the variable reactance on these pins.
The reflected signals from pins 1 and 2 are 180 degrees out of phase from each other at pin 3, the input port, and in
phase at pin 4, the output port. The signals add together at the output port, and cancel at the input port. This has a
net effect of a minimal loss broadband phase shift network, with the output signal shifted in phase by the varying
reactance of the varactor diode / inductor networks.
The other three phase shifter networks function in a manner identical to the T1 circuit described above. Attenuator
networks between T1 and T2, T3 and T4 serve to provide consistent RF impedance matching as the varactor control
voltage is changed. Amplifier U19 provides gain and isolation between the sections of the phase shift network.