User's Manual

Model 1150A DVOR
Rev. - November, 2008
This document contains proprietary information and such information may not be disclosed
to others for any purposes without written permission from SELEX Sistemi Integrati Inc.
2-11
Voltage regulator U2 provides a +5 volt source for U4, the carrier loop controller IC. By using a separate +5V
s
ource, the sensitive charge pump output of U4 will not be affected by other VOR system +5V circuitry.
U4 provides a number of functions. It contains the programmable divider network used to set the operating
frequency of the phase locked loop, the phase comparator, the charge pump output used to drive the loop low pass
filter, lock detection circuitry, and a programmable divider on the loop reference frequency input. In this
application, since the reference frequency is 200 KHz applied to the oscillator input of U4, the reference divider is
programmed to divide the reference frequency by 4 to provide a 50 KHz loop reference frequency.
The variable frequency feedback signal from U10 is applied to the variable frequency input (Fin) of U4. This signal
is divided in a programmable divider to match the loop reference frequency, or 50.00 KHz. For example, if the
desired VOR channel is 113.000 MHz, the programmable divider will divide the incoming RF signal by 2,260. If
the desired channel is 117.950 MHz, the programmable divider will divide this input signal by 2,350.
After the variable RF signal is divided by the programmable divider, it is applied to U4’s internal phase comparator,
where it is compared to the 200.00 KHz reference signal. If the variable RF signal phase slightly lags the 200.00
KHz reference signal, U4’s charge pump output (CPO) is driven high, causing the voltage at the VCO control input
to increase. This will increase the frequency of the VCO, until the phase difference between the variable signal and
the reference signal is near zero. In the same manner, if the variable RF signal phase slightly leads the 200.00 KHz
reference signal phase, the charge pump output is driven low, causing the voltage at the VCO control input to
reduce, lowering the VCO output frequency, until the difference between the variable signal phase and the reference
signal phase are near zero. This has the effect of locking the output frequency to the precision 200.00 KHz
reference signal, multiplied in frequency by the number programmed into U4’s input divider network.
When the variable phase and reference phase within the loop controller IC are locked together, U4 provides an
output indicating that the phase locked loop synthesizer is in the locked state.
The information for programming the dividers within U4 is provided by the SPI interface bus from the audio
generator CCA. The audio generator CCA determines the channel frequency, calculates the required programmable
divider settings, and creates the serial data stream, clock signals, and data latch signals used to program U4, the
synthesizer loop controller IC.
When U4 determines that the loop is indeed locked, it switches the lock detect output high, illuminating CR3 on the
012262 interface board and providing a logic low output used to indicate carrier RF generation loop lock. If U4
senses that the carrier RF generation loop is unlocked, it switches the logic high output to a logic low indicating loop
unlock, extinguishes CR3, and the signal is sent to the audio generator to re-initialize the loop controller IC.
RF signal is routed through the signal splitter / attenuator parts R15, R17, and R26 where it is applied to the carrier
frequency divider U5. U5 is actually the same type part as U4, the carrier synthesizer loop controller IC. In this
application, however, U5 is used simply as a frequency divider, dividing the RF signal by 1280. U5 is programmed
by the audio generator CCA to operate as a fixed divide by 1280, with the output provided at pin 14, FO/LD. This
output is a short duration pulse, occurring at 1/1280 of the programmed VOR channel frequency. This pulse is
applied to flip flop U8:A, where it is divided by two to create a square wave signal at the carrier frequency divided
by 2560. This output is used elsewhere in the VOR system to monitor the frequency of the carrier synthesizer.
The output of amplifier U11 is split in a resistive power splitter / attenuator combination and is used in four separate
functions. RF output is taken from R53, applied to amplifier U18, then routed through an attenuator (R83, R84,
R85) where it is applied to phase detector HY1 as the reference RF phase for the carrier phase correction loop (not
to be confused with the carrier RF generation loop). RF output is taken from R50 and routed via jumper J2 to the
carrier phase shift network.
RF signal is routed through R55 and C45 to E1. E1 is a one pin connector that provides a RF feed through to the
012162 interface CCA. The RF signal from E1 is amplified by U6 (on the 012162 board), passes through an
attenuator made up of R14, R15, and R16, then made available on the front panel of the synthesizer module via J2,
Carrier Frequency Output.