User's Manual

Model 1150A DVOR
2-10 Rev. - November, 2008
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to others for any purposes without written permission from SELEX Sistemi Integrati Inc.
The output of Y1 routes to buffers U15:A and U15:B. The buffer U15:B routes to 1/2 of a dual decade counter
U16:A. This counter divides the input signal by 5, then routes it to U16:B, the other half of this IC. Here it is
divided by 10 again, creating a 200 KHz signal. The 200 KHz signal is provided to the PLL circuit on the 012263
CCA. The 200 KHz signal is used as a reference for the PLL circuit.
The output of buffer U15:A is the 10.000 MHz reference clock for the direct digital synthesizer (DDS), U17.
Figure 2-5 Carrier RF Generation Loop
2.3.2.1.2.2
Carrier PLL Synthesizer Circuitry
Refer to Figure 2-5, the Carrier RF Generation Loop block diagram. The carrier radio frequency is generated by a
phase lock loop synthesizer. The loop is comprised of a voltage controlled oscillator, or VCO, buffer amplifiers and
power splitters, and a loop controller IC with an SPI interface bus.
Voltage regulator U6 provides a +12V supply to Q1 for a low-noise +10V line used by the VCO, U9. This regulator
provides isolation from sources of power supply noise which would adversely affect the RF spectrum of the VCO
output.
U9, the VCO is an oscillator that generates a RF signal, the frequency of which is proportional to a control voltage at
pin 5, the tuning input. The output of this oscillator is applied to a cascode buffer amplifier circuit composed of Q2,
Q3, R30 – R32, R34, R36, R37, C27, C30, C35, C36 and L3. The amplifier provides low phase noise and good
isolation to external noise influences. Buffer amplifier U11 provides gain to bring the signal back up to
approximately +15 dBm, as well as providing additional reverse isolation to prevent signal degradation from noise.
The output of the cascode buffer amplifier is applied to a resistive power splitter / attenuator combination made up
of R35, R38 – R43. The output of R35 is amplified by U10, where it is again split and attenuated. The output of
R24 is applied to U4, the synthesizer loop controller IC. The output from R43 is amplified by U11.